Optimal clocking and enhanced testability for high-performance self-resetting domino pipelines

Proceedings - 20th Anniversary Conference on Advanced Research in VLSI, ARVLSI 1999

Volumn , Issue , 1999, Pages 200-214

  Dooply, Ayoob E ^a   Yun, Kenneth Y ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

PIPELINES; VLSI CIRCUITS;

CLOCK RATE; DOMINO CIRCUIT; MULTIPLE STUCK FAULTS; PIPELINE STAGES; PRE-CHARGE; TESTABILITY; TIME BORROWING; TIMING REQUIREMENTS;

CLOCKS;

EID: 84961968044     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ARVLSI.1999.756049     Document Type: Conference Paper

References (12)

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