A 1.3 Gsample/s 10-tap full-rate variable-latency self-timed FIR filter with clocked interfaces

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2002, Pages 60-61+444+51

  Tierno, Jose ^a   Rylyakov, Alexander ^a   Rylov, Sergey ^a   Singh, Montek ^a   Ampadu, Paul ^a   Nowick, Steven ^a   Immediato, Michael ^a   Gowda, Sudhir ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; ENERGY DISSIPATION; FIR FILTERS; INTERFACES (COMPUTER); MICROPROCESSOR CHIPS; THROUGHPUT;

SELF-TIMED CONTROL CIRCUITS;

DIGITAL SIGNAL PROCESSING;

EID: 0036113496     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. Digital FIR filters for high speed PRML disk read channels
2. A 2.3 GSample/s 10-tap digital FIR filter for magnetic recording read channels
3. Fine-grain pipelined asynchronous adders for high-speed DSP applications