Satisfiability-based automatic test program generation and design for testability for microprocessors

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 15, Issue 5, 2007, Pages 518-530

  Lingappan, Loganathan ^b   Jha, Niraj K ^a,c  

^a IEEE   (United States)

^b NVIDIA   (United States)

^c Princeton University   (United States)

Author keywords

Design for testability; Microprocessor; Satisfiability; Test generation; Test program

Indexed keywords

AUTOMATIC TEST PROGRAMS; MICROARCHITECTURAL DESCRIPTION; SATISFIABILITY (SAT); TEST GENERATION;

BOOLEAN ALGEBRA; COMPUTER ARCHITECTURE; DESIGN FOR TESTABILITY; EMBEDDED SYSTEMS; FEATURE EXTRACTION; INPUT OUTPUT PROGRAMS;

MICROPROCESSOR CHIPS;

EID: 34249786276     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2007.896908     Document Type: Article

References (32)

1. J. Shen and J. A. Abraham, "Native mode functional test generation for processors with applications to self test and design validation," in Proc. Int. Test Conf., 1998, pp. 990-999.
2. K. Batcher and C. Papachristou, "Instruction randomization self test for processor cores," in Proc. VLSI Test Symp., 1999, pp. 34-40.
3. P. Parvathala, K. Maneparambil, and W. Lindsay, "FRITS - A micro-processor functional BIST method," in Proc. Int. Test Conf., 2002, pp. 590-598.
4. W. C. Lai, A. Krstic, and K. T. Cheng, 'Test program synthesis for path delay faults in microprocessor cores," in Proc. Int. Test Conf., 2000, pp. 1080-1089.
5. L. Chen, S. Ravi, A. Raghunathan, and S. Dey, "A scalable software-based self-test methodology for programmable processors," in Proc. Design Autom. Conf., 2003, pp. 548-553.
6. C. Wen, L. C. Wang, K. T. Cheng, W. T. Liu, and C. C. Chen, "On a software-based self-test methodology and its application," in Proc. VLSI Test Symp., 2005, pp. 107-113.
7. A. Paschalis and D. Gizopoulos, "Effective software-based self-test strategies for on-line periodic testing of embedded processors," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 24, no. 1, pp. 88-99, Jan. 2005.
8. N. Kranitis, A. Paschalis, D. Gizopoulos, and G. Xenoulis, "Software-based self-testing of embedded processors," IEEE Trans. Comput., vol. 54, no. 4, pp. 461-475, Apr. 2005.
9. F. Corno, G. Cumani, M. S. Reorda, and G. Squillero, "Fully automatic test program generation for microprocessor cores," in Proc. Design, Autom. Test Eur. Conf., 2003, pp. 1006-1011.
10. S. Gurumurthy, S. Vasudevan, and J. A. Abraham, "Automated mapping of pre-computed module-level test sequences to processor instructions," in Proc. Int. Test Conf., 2005, p. 10.
11. M. Psarakis, D. Gizopoulos, M. Hatzimihail, A. Paschalis, A. Raghunathan, and S. Ravi, "Systematic software-based self-test for pipelined processors," in Proc. Design Autom. Conf., 2006, pp. 393-398.
12. P. Vishakantaiah, J. A. Abraham, and D. G. Saab, "CHEETA: Composition of hierarchical sequential tests using ATKET," in Proc. Int. Test Conf., 1993, pp. 606-615.
13. R. S. Tupuri, A. Krishnamachary, and J. A. Abraham, 'Test generation for gigahertz processors using an automatic functional constraint extractor," in Proc. Design Autom. Conf., 1999, pp. 647-652.
14. Z. Navabi, VHDL: Analysis and Modeling of Digital Systems. New York: McGraw-Hill, 1993.
15. K. Kambe, M. Inoue, and H. Fujiwara, "Efficient template generation for instruction-based self-test of processor cores," in Proc. Asian Test Symp., 2004, pp. 444-449.
16. B. T. Murray and J. P. Hayes, "Hierarchical test generation using precomputed tests for modules," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 9. no. 6, pp. 594-603, Jun. 1990.
17. S. Bhatia and N. K. Jha, "Integration of hierarchical test generation with behavioral synthesis of controller and data path circuits," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 6, no. 4, pp. 608-619, Dec. 1998.
18. I. Ghosh, A. Raghunathan, and N. K. Jha, "A design for testability technique for register-transfer level circuits using control/data flow extraction," IEEE Trans. Comput-Aided Design Integr. Circuits Syst., vol. 17, no. 8, pp. 706-723, Aug. 1998.
19. S. Ravi and N. K. Jha. "Fast test generation for circuits with RTL and gate-level views," in Proc. Int. Test Conf., 2001, pp. 1068-1077.
20. I. Ghosh and M. Fujita, "Automatic test pattern generation for functional register-transfer level circuits using assignment decision diagrams," IEEE Trans. Comput.-Aided Design Integr: Circuits Syst., vol. 20, no. 3, pp. 402-415, Mar. 2001.
21. V. Chaiyakul, D. D. Gajski, and L. Ramachandran, "High level transformations for minimizing syntactic variance," in Proc. Design Autom Conf., 1993, pp. 413-418.
22. L. Lingappan, S. Ravi, and N. K. Jha, "Satisfiability-based test generation for nonseparable RTL controller-datapath circuits," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 25, no. 3, pp. 544-557, Mar. 2006.
23. L. Lingappan and N. K. Jha, "Unsatisfiability based efficient design for testability solution for register-transfer level circuits," in Proc. VLSI Test Symp., 2005. pp. 418-423.
24. L. Lingappan and N. K. Jha, "Improving the performance of automatic sequential test generation by targeting hard-to-test faults," in Proc. Int. Conf. VLSI Design, 2006, pp. 431-436.
25. V. Chaiyakul and D. D. Gajski, "Assignment decision diagram for high-level synthesis," Dept. Inf. Comput. Sci., Univ. Calif., Irvine, 1992.
26. M. Davis, G. Logemann, and D. Loveland, "A machine program for theorem proving," Commun. ACM, vol. 5, pp. 394-397, 1962.
27. L. Zhang and S. Malik, "The quest for efficient Boolean satisfiability solvers," in Proc. Int. Conf. Comput.-Aided Verification, 2002, pp. 17-36.
28. L. Zhang and S. Malik, "Validating SAT solvers using an independent resolution-based checker: Practical implementations and other applications," in Proc. Design, Autom. Test Eur. Conf., 2003, pp. 10880-10885.
29. N. Een and N. Sorrenson, "An extensible SAT-solver," in Proc. Int. Conf. Theory Appl. Satisfiability Test., 2003, pp. 502-518.
30. Synopsys Inc., Mountain View, CA, "Design compiler," 2007.
31. X. Lin, I. Pomeranz, and S. M. Reddy, "Full scan fault coverage with partial scan," in Proc. Design, Autom. Test Eur. Conf., 1999, pp. 468-472.
32. H. K. Lee and D. S. Ha, "Hope: An efficient parallel fault simulator for synchronous sequential circuits," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 15, no. 9, pp. 1048-1058, Sep. 1996.