Unsatisfiability based efficient design for testability solution for register-transfer level circuits

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2005, Pages 418-423

  Lingappan, Loganathan ^a   Jha, Niraj K ^a  

^a Princeton University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TEST PATTERN GENERATION TOOLS; FAULT COVERAGES; GREEDY ALGORITHMS; MODULE UNDER TESTS; ORDERS OF MAGNITUDE; REGISTER TRANSFER LEVEL; SEQUENTIAL TESTS; TEST GENERATIONS;

AUTOMATIC TEST PATTERN GENERATION; FORMAL LOGIC; TESTING; VLSI CIRCUITS;

DESIGN FOR TESTABILITY;

EID: 34249830054     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2005.88     Document Type: Conference Paper

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