Automated mapping of pre-computed module-level test sequences to processor instructions

Proceedings - International Test Conference

Volumn 2005, Issue , 2005, Pages 294-303

  Gurumurthy, Sankar ^a   Vasudevan, Shobha ^a   Abraham, Jacob A ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTED TEST SEQUENCE; DEFECT COVERAGE; LOGIC PROPERTY;

AUTOMATIC TESTING; COMPUTATION THEORY; FAULT TREE ANALYSIS; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS;

BUFFER STORAGE;

EID: 33847103496     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2005.1583987     Document Type: Conference Paper

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