Integration of hierarchical test generation with behavioral synthesis of controller and data path circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 6, Issue 4, 1998, Pages 608-619

  Bhatia, Sandeep ^a,b   Jha, Niraj K ^a,c  

^a IEEE   (United States)

^b Design Systems   (United States)

^c PRINCETON UNIVERSITY   (United States)

Author keywords

Controller data path testing; Hierarchical testability; High level synthesis; Synthesis for testability

Indexed keywords

CONTROL EQUIPMENT; CONTROL SYSTEM SYNTHESIS; CONTROLLABILITY; PIPELINE PROCESSING SYSTEMS;

DATA PASS CIRCUITS;

HIERARCHICAL SYSTEMS;

EID: 0032287847     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.736134     Document Type: Article

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