Instruction randomization self test for processor cores

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1999, Pages 34-40

  Batcher, Ken ^a   Papachristou, Christos ^a  

^a CASE WESTERN RESERVE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; AUTOMATIC TESTING; BUILT-IN SELF TEST; COMPUTER ARCHITECTURE; COMPUTER SOFTWARE; DESIGN FOR TESTABILITY; EMBEDDED SYSTEMS; ERROR ANALYSIS; ERROR DETECTION; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS;

EMBEDDED PROCESSOR CORES; FAULT ANALYSIS; INSTRUCTION RANDOMIZATION SELF TEST; ON-CHIP TEST HARDWARE; STUCK AT FAULT COVERAGE;

INTEGRATED CIRCUIT TESTING;

EID: 0032691811     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (21)