Improving the performance of automatic sequential test generation by targeting hard-to-test faults

Proceedings of the IEEE International Conference on VLSI Design

Volumn 2006, Issue , 2006, Pages 431-436

  Lingappan, Loganathan ^a   Jha, Niraj K ^a  

^a Princeton University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TEST PATTERN GENERATION (ATPG); BOOLEAN SATISFIABILITY; SEQUENTIAL TEST GENERATION; STUCK-AT FAULTS;

BOOLEAN ALGEBRA; COMPUTATIONAL COMPLEXITY; FAULT TOLERANT COMPUTER SYSTEMS; MATHEMATICAL MODELS; VECTORS;

SEQUENTIAL CIRCUITS;

EID: 33748554046     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSID.2006.104     Document Type: Conference Paper

References (17)

1. N. K. Jha and S. Gupta, Testing of Digital Systems. Cambridge University Press, Cambridge, 2003.
2. K. T. Cheng, "Gate-level test generation for sequential circuits," ACM Trans. Design Automation of Electronic Systems, vol. 1, pp. 405-442, Oct. 1996.
3. T. Larrabee, "Test pattern generation using Boolean satisfiability," IEEE Trans. Computer-Aided Design, vol. 11, pp. 14-15, Jan. 1992.
4. P. Stephan, R. K. Brayton, and A. Sangiovanni-Vincentelli, "Combinational test pattern generation using satisfiability," IEEE Trans. Computer-Aided Design, vol. 15, pp. 1167-1176, Sept. 1996.
5. E. Gizdarski and H. Fujiwara, "SPIRIT: A highly robust combinational test generation algorithm," IEEE Trans. Computer-Aided Design, vol. 21, pp. 1446-1458, Dec. 2002.
6. P. Tafertshofer and A. Ganz, "SAT based ATPG using fast justification and propagation in the implication graph," in Proc. Int. Conf. Computer-Aided Design, pp. 139-146, Nov. 1999.
7. H. Konuk and T. Larrabee, "Explorations of sequential ATPG using Boolean satisfiability," in Proc. VLSI Test Symp., pp. 85-90, Apr. 1993.
8. L. Lingappan, S. Ravi, and N. K. Jha, "Test generation for non-separable RTL controller-datapath circuits using a satisfiability based approach," in Proc. Int. Conf. Computer Design, pp. 187-193, Oct. 2003.
9. M. R. Prasad, M. S. Hsiao, and J. Jain, "Can SAT be used to improve sequential ATPG methods?" in Proc. Int. Conf. VLSI Design, pp. 585-590, Jan. 2004.
10. X. Lin, I. Pomeranz, and S. M. Reddy, "Techniques for improving the efficiency of sequential circuit test generation," in Proc. Int. Conf. Computer-Aided Design, pp. 147-151, Nov. 1999.
11. M. S. Hsiao, E. M. Rudnick, and J. H. Patel, "Sequential circuit test generation using dynamic state traversal," in Proc. European Design and Test Conf., pp. 22-28, Mar. 1997.
12. M. Davis, G. Logemann, and D. Loveland, "A machine program for theorem proving," Comm. ACM, vol. 5, pp. 394-397, 1962.
13. X. Chen and M. L. Bushnell, "Dynamic state and objective learning for sequential circuit automatic test generation using decomposition equivalence," in Proc. Int. Symp. Fault Tolerant Computing, pp. 446-455, June 1994.
14. B. T. Murray and J. P. Hayes, "Hierarchical test generation using precomputed tests for modules," IEEE Trans. Computer-Aided Design, vol. 9, pp. 594-603, June 1990.
15. S. Ravi, G. Lakshminarayana, and N. K. Jha, "TAO: Regular expression based high-level testability analysis and optimization," in Proc. Int. Test Conf., pp. 331-340, Oct. 1998.
16. I. Ghosh, A. Raghunathan, and N. K. Jha, "Hierarchical test generation and design for testability methods for ASPPs and ASIPs," IEEE Trans. Computer-Aided Design, vol. 18, pp. 357-370, Mar. 1999.
17. S. Ravi, T. Ghosh, R. K. Roy, and S. Dey, "Controller resynthesis for testability enhancement of RTL controller/data path circuits," in Proc. Int. Conf. VLSI Design, pp. 193-198, Jan. 1998.