A scalable software-based self-test methodology for programmable processors

Proceedings - Design Automation Conference

Volumn , Issue , 2003, Pages 548-553

  Chen, Li ^a   Ravi, Srivaths ^b   Raghunathan, Anand ^b   Dey, Sujit ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b NEC LABORATORIES AMERICA   (United States)

Author keywords

At speed test; Manufacturing test; Microprocessor; Scalabihty; Software based self test; Test program

Indexed keywords

COMPUTER SOFTWARE; CONTROLLABILITY; MICROPROCESSOR CHIPS; REGRESSION ANALYSIS;

PROGRAMMABLE PROCESSORS;

PROGRAM PROCESSORS;

EID: 0042134725     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/775972.775973     Document Type: Conference Paper

References (21)

1. D. Wu et al., "Can scan achieve the quality level we are looking for?" Panel session, Proc. Intl. Test Conf., Baltimore, MD, Oct 2002, pp. 1194-1199.
2. J. Shen and J. A. Abraham, "Native mode functional test generation for processors with applications to self test and design validation," Proc. Intl. Test Conf., Washington DC, Oct. 1998, pp. 990-999.
3. K. Batcher and C. Papachristou, "Instruction randomization self test for processor cores," Proc. 17th IEEE VLSI Test Symp., Dana Point, CA, April 1999, pp. 34-40.
4. P. Parvathala, K. Maneparambil, and W. Lindsay, "FRITS - A microprocessor functional BIST method," Proc. Intl Test Conf., Baltimore, MD, Oct 2002, pp. 590-598.
5. L. Chen and S. Dey, "DEFUSE: A Deterministic Functional Self-Test Methodology for Processors," Proc. 18th IEEE VLSI Test Symp., Montreal, Canada, May 2000, pp. 255-262.
6. L. Chen and S. Dey, "Software-based self-testing methodology for processor cores," IEEE Trans. Computer-Aided Design, vol.20, no.3, March 2001, pp. 369-380.
7. W.-C. Lai, A. Krstic, and K.-T. Cheng, "On testing the path delay faults of a microprocessor using its instruction set," Proc. 18th VLSI Test Symp., Montreal, Canada, May 2000, pp. 15-20.
8. L. Chen, X. Bai, and S. Dey, "Testing for interconnect crosstalk defects using on-chip embedded processor cores," J. Electronic Testing: Theory and Applications, vol.18, (no.4), August 2002, pp. 529-538.
9. L. Chen and S. Dey, "Software-based diagnosis for processors," Proc. 39th Design Automation Conf., New Orleans, LA, June 2002, pp. 259-262.
10. N. Kranitis, D. Gizopoulos, A. Paschalis, Y. Zorian, "Instruction-based self-testing of processor cores," Proc. 20th VLSI Test Symp., Monterey, CA, April 2002, pp. 223-228.
11. S. Almukhaizim, P. Petrov, and A. Orailoglu, "Low-cost, software-based self-test methodologies for performance faults in processor control subsystems," IEEE Custom Integrated Circuits Conf., San Diego, CA, May 2001, pp. 263-266.
12. P. Vishakantaiah, J. Abraham, and M. Abadir, "Automatic test knowledge extraction from VHDL (ATKET)," Proc. 29th Design Automation Conf., Anaheim, CA, June 1992, pp. 273-278.
13. R. Tupuri, A. Krishnamachary, and J. Abraham, "Test Generation for Gigahertz Processors Using an Automatic Functional Constraint Extractor," Proc. 36th Design Automation Conf., New Orleans, LA, June 1999, pp. 647-652.
14. W.-C. Lai, Embedded Software-Based Self-Test for System-on-a-Chip Design, PhD thesis, Univ. California at Santa Barbara, March 2002.
15. W.-C. Lai, A. Krstic, and K.-T. Cheng, "Test program synthesis for path delay faults in microprocessor cores," Proc. Int. Test Conf., Atlantic City, NJ, Oct. 2000, pp. 1080-1089.
16. R. Tupuri and J. Abraham, "A Novel Functional Test Generation Method for Processors using Commercial ATPG," Proc. Intl. Test Conf., Washington, DC, Nov. 1997, p.743-752.
17. W.N. Venables and B.D. Ripley, Modern Applied Statistics with S-PLUS, Springer-Verlag, 1998.
18. http://www.tensilica.com/xtensa_overview_handbook.pdf, Xtensa™ Microprocessor Overview Handbook, Tensilica Inc, August 2001.
19. Design Compiler™, Synopsys Inc., http://www.synopsys.com
20. Modelsim™, Model Technologies Inc., http://www.model.com
21. FlexTest™, Mentor Graphics Corp., http://www.mentor.com