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Volumn 20, Issue 3, 2001, Pages 402-415
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Automatic test pattern generation for functional register-transfer level circuits using assignment decision diagrams
a,b
a
IEEE
(United States)
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Author keywords
Algorithm; ATPG; Data structure; HDL; RTL; Testing
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Indexed keywords
ASSIGNMENT DECISION DIAGRAMS;
AUTOMATIC TEST PATTERN GENERATION;
REGISTER TRANSFER LEVEL CIRCUITS;
ALGORITHMS;
COMPUTER AIDED DESIGN;
COMPUTER HARDWARE DESCRIPTION LANGUAGES;
COMPUTER SIMULATION;
DATA STRUCTURES;
DESIGN FOR TESTABILITY;
FAILURE ANALYSIS;
INTEGRATED CIRCUIT TESTING;
LOGIC DESIGN;
SEQUENTIAL CIRCUITS;
INTEGRATED CIRCUIT LAYOUT;
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EID: 0035271698
PISSN: 02780070
EISSN: None
Source Type: Journal
DOI: 10.1109/43.913758 Document Type: Article |
Times cited : (57)
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References (39)
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