Automatic test pattern generation for functional register-transfer level circuits using assignment decision diagrams

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 20, Issue 3, 2001, Pages 402-415

  Ghosh, Indradeep ^a,b   Fujita, Masahiro ^a,c  

^a IEEE   (United States)

^b FUJITSU LABORATORIES OF AMERICA   (United States)

^c UNIVERSITY OF TOKYO   (Japan)

Author keywords

Algorithm; ATPG; Data structure; HDL; RTL; Testing

Indexed keywords

ASSIGNMENT DECISION DIAGRAMS; AUTOMATIC TEST PATTERN GENERATION; REGISTER TRANSFER LEVEL CIRCUITS;

ALGORITHMS; COMPUTER AIDED DESIGN; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION; DATA STRUCTURES; DESIGN FOR TESTABILITY; FAILURE ANALYSIS; INTEGRATED CIRCUIT TESTING; LOGIC DESIGN; SEQUENTIAL CIRCUITS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0035271698     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.913758     Document Type: Article

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