Efficient template generation for instruction-based self-test of processor cores

Proceedings of the Asian Test Symposium

Volumn , Issue , 2004, Pages 152-157

  Kambe, Kazuko ^a   Inoue, Michiko ^a   Fujiwara, Hideo ^a  

^a NARA INSTITUTE OF SCIENCE AND TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DETECTABLE FAULT SETS; FUALT COVERAGE; INPUT SPACES; TEMPLATE GENERATION;

BUILT-IN SELF TEST; CONSTRAINT THEORY; FAULT TOLERANT COMPUTER SYSTEMS; FUNCTIONS; NETWORKS (CIRCUITS); PROCESS CONTROL; RANDOM PROCESSES;

MICROPROCESSOR CHIPS;

EID: 13244291306     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ATS.2004.39     Document Type: Conference Paper

References (8)

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