-
1
-
-
0036927918
-
Charge trapping in high k gate dielectric stacks
-
S. Zafar, A. Callegari, E. Gusev, and V. Fischetti, "Charge trapping in high k gate dielectric stacks," in IEDM Tech. Dig., 2002, pp. 517-520.
-
(2002)
IEDM Tech. Dig
, pp. 517-520
-
-
Zafar, S.1
Callegari, A.2
Gusev, E.3
Fischetti, V.4
-
2
-
-
0037634587
-
Evaluation of the positive biased temperature stress stability in HfSiON gate dielectrics
-
Dallas, TX
-
A. Shanware, M. Visokay, J. Chambers, A. Rotondaro, H. Bu, M. Bevan, R. Khamankar, S. Aur, P. Nicollian, J. McPherson, and L. Colombo, "Evaluation of the positive biased temperature stress stability in HfSiON gate dielectrics," in Proc. IRPS, Dallas, TX, 2003, pp. 208-213.
-
(2003)
Proc. IRPS
, pp. 208-213
-
-
Shanware, A.1
Visokay, M.2
Chambers, J.3
Rotondaro, A.4
Bu, H.5
Bevan, M.6
Khamankar, R.7
Aur, S.8
Nicollian, P.9
McPherson, J.10
Colombo, L.11
-
3
-
-
0043201362
-
2 MOSFETs
-
Jun
-
2 MOSFETs," IEEE Trans. Electron Devices, vol. 50, no. 6, pp. 1517-1524, Jun. 2003.
-
(2003)
IEEE Trans. Electron Devices
, vol.50
, Issue.6
, pp. 1517-1524
-
-
Onishi, K.1
Choi, R.2
Kang, C.S.3
Cho, H.-J.4
Kim, Y.H.5
Nieh, R.6
Han, J.7
Krishnan, S.8
Akbar, M.9
Lee, J.10
-
4
-
-
84955276085
-
2 gate dielectrics
-
2 gate dielectrics," in Proc. IEEE IRPS, 2003, pp. 41-45.
-
(2003)
Proc. IEEE IRPS
, pp. 41-45
-
-
Kerber, A.1
Cartier, E.2
Ragnarsson, L.A.3
Rosmeulen, M.4
Pantisano, L.5
Degraeve, R.6
Kauerauf, T.7
Grocseneken, G.8
Maes, H.E.9
Schwalke, U.10
-
5
-
-
17644439238
-
2 gate dielectrics
-
Washington, DC
-
2 gate dielectrics," in IEDM Tech. Dig., Washington, DC, 2003, pp. 939-942.
-
(2003)
IEDM Tech. Dig
, pp. 939-942
-
-
Shanware, A.1
Visokay, M.2
Chambers, J.3
Rotondaro, A.4
McPherson, J.5
Colombo, L.6
Brown, G.7
Lee, C.8
Kim, Y.9
Gardner, M.10
Murto, R.11
-
6
-
-
3042561377
-
2 and threshold voltage instability in MOSFETs
-
2 and threshold voltage instability in MOSFETs," in Proc. IRPS, 2004, pp. 601-602.
-
(2004)
Proc. IRPS
, pp. 601-602
-
-
Shen, C.1
Yu, H.Y.2
Wang, X.P.3
Li, M.-F.4
Yeo, Y.-C.5
Chan, D.S.H.6
Bera, K.L.7
Kwong, D.L.8
-
7
-
-
20444480929
-
2 gate dielectrics and frequency dependence of dynamic BTI in MOSFETs
-
2 gate dielectrics and frequency dependence of dynamic BTI in MOSFETs," in IEDM Tech. Dig., 2004, pp. 733-736.
-
(2004)
IEDM Tech. Dig
, pp. 733-736
-
-
Shen, C.1
Li, M.F.2
Wang, X.P.3
Yu, H.Y.4
Feng, Y.P.5
Lim, A.T.-L.6
Yeo, Y.-C.7
Chan, H.8
Kwong, D.L.9
-
8
-
-
21644465398
-
Intrinsic characteristics of high-κ devices and implications of fast transient charging effects (FTCE)
-
B. Lee, C. Young, R. Choi, J. Sim, G. Bersuker, C. Kang, R. Harris, G. Brown, K. Matthews, S. Song, N. Moumen, J. Barnett, P. Lysaght, K. Choi, H. Wen, C. Huffman, H. Alshareef, P. Majhi, S. Gopalan, J. Peterson, P. Kirsh, H.-J. Li, J. Gutt, M. Gardner, H. Huff, P. Zeitzoff, R. Murto, L. Larson, and C. Ramiller, "Intrinsic characteristics of high-κ devices and implications of fast transient charging effects (FTCE)," in IEDM Tech. Dig., 2004, pp. 859-862.
-
(2004)
IEDM Tech. Dig
, pp. 859-862
-
-
Lee, B.1
Young, C.2
Choi, R.3
Sim, J.4
Bersuker, G.5
Kang, C.6
Harris, R.7
Brown, G.8
Matthews, K.9
Song, S.10
Moumen, N.11
Barnett, J.12
Lysaght, P.13
Choi, K.14
Wen, H.15
Huffman, C.16
Alshareef, H.17
Majhi, P.18
Gopalan, S.19
Peterson, J.20
Kirsh, P.21
Li, H.-J.22
Gutt, J.23
Gardner, M.24
Huff, H.25
Zeitzoff, P.26
Murto, R.27
Larson, L.28
Ramiller, C.29
more..
-
9
-
-
0141649545
-
High mobility MISFET with low trapped charge in HfSiO films
-
A. Morioka, H. Watanabe, M. Miyamura, T. Tatsumi, M. Saitoh, T. Ogura, T. Iwamoto, T. Ikarashi, Y. Saito, Y. Okada, H. Watanabe, Y. Mochiduki, and T. Mogami, "High mobility MISFET with low trapped charge in HfSiO films," in VLSI Symp. Tech. Dig., 2003, pp. 165-166.
-
(2003)
VLSI Symp. Tech. Dig
, pp. 165-166
-
-
Morioka, A.1
Watanabe, H.2
Miyamura, M.3
Tatsumi, T.4
Saitoh, M.5
Ogura, T.6
Iwamoto, T.7
Ikarashi, T.8
Saito, Y.9
Okada, Y.10
Watanabe, H.11
Mochiduki, Y.12
Mogami, T.13
-
10
-
-
4544326575
-
High mobility and excellent electrical stability of MOSFETs using a novel HfTaO gate dielectric
-
Honolulu, HI
-
X. Yu, C. Zhu, X. Wang, M. Li, A. Chin, A. Du, W. Wang, and D.-L. Kwong, "High mobility and excellent electrical stability of MOSFETs using a novel HfTaO gate dielectric," in VLSI Symp. Tech. Dig., Honolulu, HI, 2004, pp. 110-111.
-
(2004)
VLSI Symp. Tech. Dig
, pp. 110-111
-
-
Yu, X.1
Zhu, C.2
Wang, X.3
Li, M.4
Chin, A.5
Du, A.6
Wang, W.7
Kwong, D.-L.8
-
11
-
-
33645471189
-
Tuning effective metal gate work function by a novel gate dielectric HfLaO for nMOSFETs
-
Jan
-
X. P. Wang, M.-F. Li, C. Ren, X. F. Yu, C. Shen, H. H. Ma, A. Chin, C. X. Zhu, J. Ning, M. B. Yu, and D.-L. Kwong, "Tuning effective metal gate work function by a novel gate dielectric HfLaO for nMOSFETs," IEEE Electron Device Lett., vol. 27, no. 1, pp. 31-33, Jan. 2006.
-
(2006)
IEEE Electron Device Lett
, vol.27
, Issue.1
, pp. 31-33
-
-
Wang, X.P.1
Li, M.-F.2
Ren, C.3
Yu, X.F.4
Shen, C.5
Ma, H.H.6
Chin, A.7
Zhu, C.X.8
Ning, J.9
Yu, M.B.10
Kwong, D.-L.11
-
12
-
-
20444457876
-
Charge trapping in aggressively scaled metal gate/high-high-κ stacks
-
E. Gusev, V. Narayanan, S. Zafar, C. Cabrai, Jr., E. Cartier, N. Bojarczuk, A. Callegari, R. Carruthers, M. Chudzik, C. D'Emic, E. Duch, P. Jamison, P. Kozlowski, D. LaTulipe, K. Maitra, F. McFeely, J. Newbury, V. Paruchuri, and M. Steen, "Charge trapping in aggressively scaled metal gate/high-high-κ stacks," in IEDM Tech. Dig., 2004, pp. 729-732.
-
(2004)
IEDM Tech. Dig
, pp. 729-732
-
-
Gusev, E.1
Narayanan, V.2
Zafar, S.3
Cabrai Jr., C.4
Cartier, E.5
Bojarczuk, N.6
Callegari, A.7
Carruthers, R.8
Chudzik, M.9
D'Emic, C.10
Duch, E.11
Jamison, P.12
Kozlowski, P.13
LaTulipe, D.14
Maitra, K.15
McFeely, F.16
Newbury, J.17
Paruchuri, V.18
Steen, M.19
-
13
-
-
0842266673
-
-
2O) for improved MOSFET stability, in IEDM Tech. Dig., 2003, pp. 4.1.1-4.1.4.
-
2O) for improved MOSFET stability," in IEDM Tech. Dig., 2003, pp. 4.1.1-4.1.4.
-
-
-
-
14
-
-
33847750682
-
-
y/high-κ gate stack for enhanced device threshold voltage stability and performance, in IEDM Tech. Dig., 2005, pp. 696-699. no. 29.4.
-
y/high-κ gate stack for enhanced device threshold voltage stability and performance," in IEDM Tech. Dig., 2005, pp. 696-699. no. 29.4.
-
-
-
-
15
-
-
33947263035
-
-
M. Inoue, S. Tsujikawa, M. Mizutani, K. Nomura, T. Hayashi, K. Shiga, J. Yugami, J. Tsuchimoto, Y. Ohno, and M. Yoneda, Fluorine incorporation into HfSiON dielectric for Vth control and its impact on reliability for poly-Si gate pFET, in IEDM Tech. Dig., 2005, p. 17.1.
-
M. Inoue, S. Tsujikawa, M. Mizutani, K. Nomura, T. Hayashi, K. Shiga, J. Yugami, J. Tsuchimoto, Y. Ohno, and M. Yoneda, "Fluorine incorporation into HfSiON dielectric for Vth control and its impact on reliability for poly-Si gate pFET," in IEDM Tech. Dig., 2005, p. 17.1.
-
-
-
-
16
-
-
33645470424
-
Fast and slow dynamic NBTI components in p-MOSFET with SiON dielectric and their impact on device life-time and circuit application
-
T. Yang, M. F. Li, C. Shen, C. H. Ang, C. Zhu, Y.-C. Yeo, G. Samudra, S. C. Rustagi, M. B. Yu, and D. L. Kwong, "Fast and slow dynamic NBTI components in p-MOSFET with SiON dielectric and their impact on device life-time and circuit application," in VLSI Symp. Tech. Dig., 2005, pp. 92-93.
-
(2005)
VLSI Symp. Tech. Dig
, pp. 92-93
-
-
Yang, T.1
Li, M.F.2
Shen, C.3
Ang, C.H.4
Zhu, C.5
Yeo, Y.-C.6
Samudra, G.7
Rustagi, S.C.8
Yu, M.B.9
Kwong, D.L.10
-
17
-
-
27744444546
-
Fast DNBTI component in p-MOSFET with SiON dielectric
-
Nov
-
T. Yang, C. Shen, M.-F. Li, C. H. Ang, C. X. Zhu, Y.-C. Yeo, G. Samudra, S. C. Rustagi, M. B. Yu, and D.-L. Kwong, "Fast DNBTI component in p-MOSFET with SiON dielectric," IEEE Electron. Device Lett., vol. 26, no. 11, pp. 826-828, Nov. 2005.
-
(2005)
IEEE Electron. Device Lett
, vol.26
, Issue.11
, pp. 826-828
-
-
Yang, T.1
Shen, C.2
Li, M.-F.3
Ang, C.H.4
Zhu, C.X.5
Yeo, Y.-C.6
Samudra, G.7
Rustagi, S.C.8
Yu, M.B.9
Kwong, D.-L.10
-
18
-
-
21644455928
-
On-the-fly characterization of NBTI in ultra-thin gate oxide PMOSFETs
-
M. Denais, A. Bravaix, V. Huard, C. Parthasarathy, G. Ribes, F. Perrier, Y. Rey-Tauriac, and N. Revil, "On-the-fly characterization of NBTI in ultra-thin gate oxide PMOSFETs," in IEDM Tech. Dig., 2004, pp. 109-112.
-
(2004)
IEDM Tech. Dig
, pp. 109-112
-
-
Denais, M.1
Bravaix, A.2
Huard, V.3
Parthasarathy, C.4
Ribes, G.5
Perrier, F.6
Rey-Tauriac, Y.7
Revil, N.8
-
19
-
-
17644440782
-
2 gate stack for advanced CMOS devices
-
2 gate stack for advanced CMOS devices," in IEDM Tech. Dig., 2003, pp. 99-102.
-
(2003)
IEDM Tech. Dig
, pp. 99-102
-
-
Yu, H.Y.1
Kang, J.F.2
Chen, J.D.3
Ren, C.4
Hou, Y.T.5
Wháng, S.J.6
Li, M.F.7
Chan, D.S.H.8
Bera, K.L.9
Tung, C.H.10
Du, A.11
Kwong, D.-L.12
-
20
-
-
20444448462
-
Ultra-short pulse I-V characterization of the intrinsic behavior of high-κ devices
-
C. D. Young, Y. G. Zhao, M. Pendley, B. H. Lee, K. Matthews, J. H. Sim, R. Choi, G. Bersuker, and G. A. Brown, "Ultra-short pulse I-V characterization of the intrinsic behavior of high-κ devices," in Proc. SSDM, 2004, pp. 216-217.
-
(2004)
Proc. SSDM
, pp. 216-217
-
-
Young, C.D.1
Zhao, Y.G.2
Pendley, M.3
Lee, B.H.4
Matthews, K.5
Sim, J.H.6
Choi, R.7
Bersuker, G.8
Brown, G.A.9
-
21
-
-
33645462580
-
g characteristics
-
Jan
-
g characteristics," IEEE Electron Device Lett., vol. 27, no. I, pp. 55-57, Jan. 2006.
-
(2006)
IEEE Electron Device Lett
, vol.27
, Issue.I
, pp. 55-57
-
-
Shen, C.1
Li, M.-F.2
Wang, X.P.3
Yeo, Y.-C.4
Kwong, D.-L.5
-
22
-
-
28744436722
-
Single-electron emission of traps in HfSiON as high-κ gate dielectric for MOSFETs
-
C. T. Chan, C. J. Tang, C. H. Kuo, H. C. Ma, C. W. Tsai, H. C.-H. Wang, M. H. Chi, and T. Wang, "Single-electron emission of traps in HfSiON as high-κ gate dielectric for MOSFETs," in Proc. IRPS, 2005, pp. 41-44.
-
(2005)
Proc. IRPS
, pp. 41-44
-
-
Chan, C.T.1
Tang, C.J.2
Kuo, C.H.3
Ma, H.C.4
Tsai, C.W.5
Wang, H.C.-H.6
Chi, M.H.7
Wang, T.8
-
23
-
-
33947216496
-
-
C. T. Chan, C. J. Tang, T. Wang, H. C.-H. Wang, and D. D. Tang, Positive bias and temperature stress induced two-stage drain-current degradation in HfSiON nMOSFETs, in IEDM Tech. Dig., 2005, p. 22.7.
-
C. T. Chan, C. J. Tang, T. Wang, H. C.-H. Wang, and D. D. Tang, "Positive bias and temperature stress induced two-stage drain-current degradation in HfSiON nMOSFETs," in IEDM Tech. Dig., 2005, p. 22.7.
-
-
-
-
24
-
-
0037718399
-
2 dual layer gate dielectrics
-
Feb
-
2 dual layer gate dielectrics," IEEE Electron Device Lett., vol. 24, no. 2, pp. 87-89, Feb. 2003.
-
(2003)
IEEE Electron Device Lett
, vol.24
, Issue.2
, pp. 87-89
-
-
Kerber, A.1
Cartier, E.2
Pantisano, L.3
Degraeve, R.4
Kauerauf, T.5
Kim, Y.6
Hou, A.7
Groeseneken, G.8
Maes, H.9
Schwalke, U.10
-
25
-
-
0000046908
-
2
-
Sep. 15
-
2," J. Appl. Phys. (USA), vol. 58, no. 6, pp. 2252-2261, Sep. 15, 1985.
-
(1985)
J. Appl. Phys. (USA)
, vol.58
, Issue.6
, pp. 2252-2261
-
-
Nissan-Cohen, Y.1
Shappir, J.2
Frohman-Bentchkowsky, D.3
-
26
-
-
21044436652
-
2 gate dielectric
-
2 gate dielectric," Appl. Phys. Lett., vol. 86, no. 9, p. 093510, 2005.
-
(2005)
Appl. Phys. Lett
, vol.86
, Issue.9
, pp. 093510
-
-
Shen, C.1
Li, M.F.2
Yu, H.Y.3
Wang, X.P.4
Yeo, Y.-C.5
Chan, D.S.H.6
Kwong, D.-L.7
-
27
-
-
0033712799
-
New paradigm of predictive MOSFET and interconnect modeling for early circuit design
-
Online, Available
-
Y. Cao, T. Sato, D. Sylvester, M. Orshansky, and C. Hu, "New paradigm of predictive MOSFET and interconnect modeling for early circuit design," in Proc. CICC, pp. 201-204. [Online]. Available: http://www.eas.asu.edu/~ptm/
-
Proc. CICC
, pp. 201-204
-
-
Cao, Y.1
Sato, T.2
Sylvester, D.3
Orshansky, M.4
Hu, C.5
-
28
-
-
33645403754
-
NBTI impact on transistor and circuit: Models, mechanisms and scaling effects
-
Washington, DC
-
A. Krishnan, V. Reddy, S. Chakravarthi, J. Rodriguez, S. John, and S. Krishnan, "NBTI impact on transistor and circuit: Models, mechanisms and scaling effects," in IEDM Tech. Dig., Washington, DC, 2003, pp. 14-15.
-
(2003)
IEDM Tech. Dig
, pp. 14-15
-
-
Krishnan, A.1
Reddy, V.2
Chakravarthi, S.3
Rodriguez, J.4
John, S.5
Krishnan, S.6
-
29
-
-
0034315851
-
A dynamic voltage scaled microprocessor system
-
Nov
-
T. Burd, T. Pering, A. Stratakos, and R. Brodersen, "A dynamic voltage scaled microprocessor system," IEEE J. Solid-State Circuits, vol. 35, no. 11, pp. 1571-1580, Nov. 2000.
-
(2000)
IEEE J. Solid-State Circuits
, vol.35
, Issue.11
, pp. 1571-1580
-
-
Burd, T.1
Pering, T.2
Stratakos, A.3
Brodersen, R.4
-
30
-
-
21644482313
-
Charge trapping effects in HfSiON dielectrics on the ring oscillator circuit and the single stage inverter operation
-
San Francisco, CA
-
C. Kang, J. Lee, R. Choi, J. Sim, C. Young, B. Lee, and G. Bersuker, "Charge trapping effects in HfSiON dielectrics on the ring oscillator circuit and the single stage inverter operation," in IEDM Tech. Dig., San Francisco, CA, 2004, pp. 485-488.
-
(2004)
IEDM Tech. Dig
, pp. 485-488
-
-
Kang, C.1
Lee, J.2
Choi, R.3
Sim, J.4
Young, C.5
Lee, B.6
Bersuker, G.7
|