Bias-temperature instabilities of polysilicon gate HfO2 MOSFETs

IEEE Transactions on Electron Devices

Volumn 50, Issue 6, 2003, Pages 1517-1524

  Onishi, Katsunori ^a   Choi, Rino ^b   Kang, Chang Seok ^b   Cho, Hag Ju ^b   Kim, Young Hee ^b   Nieh, Renee E ^c   Han, Jeong ^b   Krishnan, Siddharth A ^b   Akbar, Mohammad Shahariar ^b   Lee, Jack C ^b  

^a IBM MICROELECTRONICS   (United States)

^b The University of Texas at Austin   (United States)

^c Samsung Austin Semiconductor   (United States)

Author keywords

Charge pumping; CMOSFETs; Hafnium; HfO2; High k gate dielectric; Polysilicon gate; Reliability; Semiconductor insulator interfaces; Surface states

Indexed keywords

ANNEALING; GATES (TRANSISTOR); HAFNIUM COMPOUNDS; POLYSILICON; THERMAL EFFECTS;

CHARGE PUMPING MEASUREMENTS;

MOSFET DEVICES;

EID: 0043201362     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2003.813522     Document Type: Article

References (37)

1. S.-H. Lo, D. A. Buchanan, Y. Taur, and W. Wang, "Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFETs," IEEE Electron Device Lett., vol. 18, pp. 209-211, May 1997.
2. J. H. Stathis and D. J. DiMaria, "Reliability projection for ultra-thin oxides at low voltage," in IEDM Tech. Dig., 1998, pp. 167-170.
3. 2 films from organo-hafnium compounds," Thin Solid Films, vol. 41, pp. 247-259, 1977.
4. J. Robertson, "Band offsets of wide-band-gap oxides and implications for future electronic devices," J. Vac. Sci. Technol. B, vol. 18, pp. 1785-1791, 2000.
5. K. J. Hubbard and D. G. Schlom, "Thermodynamic stability of binary oxides in contact with silicon," J. Mat. Res., vol. 11, pp. 2757-2776, 1996.
6. 2 MOSFET performance," in VLSI Tech. Dig., 2002, pp. 22-23.
7. 2 gate dielectrics," in VLSI Tech. Dig., 2002, pp. 12-13.
8. 2 MOSFETs by high-temperature forming gas annealing," IEEE Trans. Electron Devices, vol. 50, pp. 384-390, Feb. 2003.
9. 2," in VLSI Tech. Dig., 2002, pp. 26-27.
10. 2 gate dielectrics," in VLSI Tech. Dig., 2002, pp. 78-79.
11. 2 equivalent thickness," in IEDM Tech. Dig., 2001, pp. 137-140.
12. ss) of thermally oxidized silicon," J. Electrochem. Soc., vol. 114, pp. 266-274, 1967.
13. 2-Si interfaces," Jpn. J. Appl. Phys., vol. 18, pp. 1087-1095, 1979.
14. J. F. Zhang and W. Eccleston, "Positive bias temperature instability in MOSFETs," IEEE Trans. Electron Devices, vol. 45, pp. 116-124, Jan. 1998.
15. 2 interface," Phys. Rev. B, vol. 51, pp. 4218-4230, 1995.
16. 2 (4-5 nm)-Si interfaces during negative-bias temperature aging," J. Appl. Phys., vol. 77, pp. 1137-1148, 1995.
17. N. Kimizuka, T. Yamamoto, T. Mogami, R. Yamaguchi, K. Imai, and T. Horiuchi, "The impact of bias temperature instability for direct-tunneling ultra-thin gate oxide on MOSFET scaling," in VLSI Tech. Dig., 1999, pp. 73-74.
18. N. Kimizuka, K. Yamaguchi, K. Imai, T. Iizuka, C. T. Liu, R. C. Keller, and T. Horiuchi, "NBTI enhancement by nitrogen incorporation into ultrathin gate oxide for 0.10-μm gate CMOS generation," in VLSI Tech. Dig., 2000, pp. 92-93.
19. V. K. Reddy, A. T. Krishnan, A. Marshall, J. Rodriguez, S. Natarajan, T. A. Rost, and S. Krishnan, "Impact of negative bias temperature instability on digital circuit reliability," in Proc. IRPS, 2002, pp. 248-254.
20. E. P. Gusev, D. A. Buchanan, E. Cartier, A. Kumar, D. DiMaria, S. Guha, A. Callegari, S. Zafar, P. C. Jamison, D. A. Neumayer, M. Copel, M. A. Gribelyuk, H. Okorn-Schmidt, C. D'Emic, P. Kozlowski, K. Chan, N. Bojarczuk, L.-Å. Ragnarsson, P. Ronsheim, K. Rim, R. J. Fleming, A. Mocuta, and A. Ajmera, "Ultrathin high-K gate stacks for advanced CMOS devices," in IEDM Tech. Dig., 2001, pp. 451-454.
21. A. Kumar, T. H. Ning, M. V. Fischetti, and E. Gusev, "Hot-carrier charge trapping and reliability in high-K dielectrics," in VLSI Tech. Dig., 2002, pp. 152-153.
22. 2 MOSFETs," in IEDM Tech. Dig., 2001, pp. 659-662.
23. 2 gate dielectric MOSFETs with TaN electrode and nitridation surface preparation," in VLSI Tech. Dig., 2001, pp. 15-16.
24. 2 MOSFETs," in VLSI Tech. Dig., 2001, pp. 131-132.
25. 2 devices with polysilicon gate electrode," in Proc. IRPS, 2002, pp. 419-420.
26. 2 high-k dielectrics," in IEDM Tech. Dig., 2000, pp. 35-38.
27. J. Hauser, CVC NCSU Software, Version 3.0. Raleigh, NC: North Carolina State Univ., 1996.
28. G. Groeseneken, H. E. Maes, N. Beltrán, and R. F. Keersmaecker, "A reliable approach to charge-pumping measurements in MOS transistors," IEEE Trans. Electron Devices, vol. ED-31, pp. 42-53, Jan. 1984.
29. J. W. McPherson and D. A. Baglee, "Acceleration factors for thin gate oxide stressing," in Proc. IRPS, 1985, pp. 1-5.
30. J. C. Lee, I.-C. Chen, and C. Hu, "Modeling and characterization of gate oxide reliability," IEEE Trans. Electron Devices, vol. 35, pp. 2268-2278, Dec. 1988.
31. E. H. Nicollian and J. R. Brews, MOS Physics and Technology. New York: Wiley, 1991.
32. D. J. DiMaria, E. Cartier, and D. Arnold, "Impact ionization, trap creation, degradation, and breakdown in silicon dioxide films on silicon," J. Appl. Phys., vol. 73, pp. 3367-3384, 1993.
33. 2/Al system due to vacuum ultraviolet irradiation," J. Appl. Phys., vol. 78, pp. 6481-6490, 1995.
34. P. J. McWhorter and P. S. Winokur, "Simple technique for separating the effects of interface traps and trapped-oxide charge in metal-oxide-semi-conductor transistors," Appl. Phys. Lett., vol. 48, pp. 133-135, 1986.
35. K. Hess, I. C. Kizilyalli, and J. W. Lyding, "Giant isotope effect in hot electron degradation of metal oxide silicon devices," IEEE Trans. Electron Devices, vol. 45, pp. 406-416, Feb. 1998.
36. M. Houssa, A. Stesmans, M. Naili, and M. M. Heyns, "Charge trapping in very thin high-permittivity gate dielectric layers," Appl. Phys. Lett., vol. 77, pp. 1381-1383, 2000.
37. Y. Shi, T. P. Ma, S. Prasad, and S. Dhanda, "Polarity dependent gate tunneling currents in dual-gate CMOSFETs," IEEE Trans. Electron Devices, vol. 45, pp. 2355-2360, Nov. 1998.