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2 has been confirmed by an ab initio calculation, as reported by J. Kang, E. C. Lee, K. J. Chang, and Y. G. Jin, Appl. Phys. Lett. 84, 3894 (2004).
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21044456941
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note
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2 interfacial layer. When a positive gate voltage is applied in the stress phase, the one-electron trap energy in the high-k dielectric moves into energy gap region of the Si substrate, and tunneling becomes forbidden.
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18
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21044434163
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note
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2/dt, where 0<η<1 represents the recapture probability. As the detrapping of the first electron is very fast, the right-hand side of the equation is dominated by the first term. The value of η is not important, and therefore dropped η for simplicity.
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