HiSIM2: Advanced MOSFET model valid for RF circuit simulation

IEEE Transactions on Electron Devices

Volumn 53, Issue 9, 2006, Pages 1994-2006

  Miura Mattausch, Mitiko ^a,b   Sadachika, Norio ^b   Navarro, Dondee ^b   Suzuki, Gaku ^b,c   Takeda, Youichi ^b,d   Miyake, Masataka ^b   Warabino, Tomoyuki ^b   Mizukane, Yoshio ^b   Inagaki, Ryosuke ^e   Ezaki, Tatsuya ^b   Mattausch, Hans Jürgen ^a,b   Ohguro, Tatsuya ^e   Iizuka, Takahiro ^a,e   Taguchi, Masahiko ^e   Kumashiro, Shigetaka ^a,e   Miyamoto, Shunsuke ^a,e  

^a IEEE   (Japan)

^b HIROSHIMA UNIVERSITY   (Japan)

^c PANASONIC CORPORATION   (Japan)

^d SANYO ELECTRIC CO LTD   (Japan)

^e SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER   (Japan)

Author keywords

Compact MOSFET model; Device physics; Iterative solution; RF features; Surface potentials

Indexed keywords

COMPACT MOSFET MODELS; DEVICE PHYSICS; ITERATIVE SOLUTION; MODEL PARAMETERS; RF FEATURES;

CIRCUIT SIMULATION; ITERATIVE METHODS; SEMICONDUCTOR DEVICE MODELS; SURFACE POTENTIAL;

MOSFET DEVICES;

EID: 33947096869     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2006.880374     Document Type: Article

References (58)

1. K. Ishii, Y. Hayashi, and T. Sekigawa, "Experimental fabrication of XMOS transistors using lateral solid-phase epitaxy of CVD silicon films," Jpn. J. Appl. Phys., vol. 29, no. 4, pp. 521-523, 1990.
2. K. K. Hung, P. K. Ko, C. Hu, and Y. C. Cheng, "A physics-based MOSFET noise model for circuit simulators," IEEE Trans. Electron Devices, vol. 37, no. 5, pp. 1323-1333, May 1990.
3. BSIM4.0.0 MOSFET Model, User's Manual, Dept. Electr. Eng. Comput. Sci., Univ. California, Berkeley, CA, 2000.
4. S. E. Laux, "Simulation study of Ge n-channel 7.5 nm DGFETs of arbitrary crystallographic alignment," in IEDM Tech. Dig., 2004, pp. 135-138.
5. M. Miura-Mattausch, U. Feldmann, A. Rahm, M. Bollu, and D. Savignac, "Unified complete MOSFET model for analysis of digital and analog circuits," Proc. IEEE Trans. Comput.-Aided Des./Int. Conf. Comput. Aided Des., vol. 15, no. 1, pp. 1-7, Jan. 1996.
6. M. Miura-Mattausch, H. J. Mattausch, N. D. Arora, and C. Y. Yang, "MOSFET modeling gets physical," IEEE Circuits Devices, vol. 17, no. 6, pp. 29-36, Nov. 2001.
7. M. Miura-Mattausch, H. Ueno, M. Tanaka, H. J. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita, and N. Nakayama, "HiSIM: A MOSFET model for circuit simulation connecting circuit performance with technology," in IEDM Tech. Dig., Dec. 2002, pp. 109-112.
8. M. Miura-Mattasuch, H. Ueno, H. J. Mattausch, K. Morikawa, S. Itoh, A. Kobayashi, and H. Masuda, "100 nm-MOSFET model for circuit simulation: Challenges and solutions," IEICE Trans. Electron., vol. E86-C, no. 6, pp. 1009-1021, 2003.
9. M. Miura-Mattausch and H. Jacobs, "Analytical model for circuit simulation with quarter micron metal oxide semiconductor field effect transistors: Subthreshold characteristics," Jpn. J. Appl. Phys., vol. 29, no. 12, pp. L2279-L2282, Dec. 1990.
10. HISIM2 Users Manual, Hiroshima University, STARC, Hiroshima, Japan, 2005.
11. M. Miura-Mattausch, "MOSFET modeling beyond 100 nm technology: Challenges and perspectives," in Proc. SISPAD, 2005, p. 1.
12. S. M. Sze, Physics of Semiconductor Device. New York: Wiley, 1981.
13. S.-Y. Oh, D. E. Ward, and R. W. Dutton, "Transient analysis of MOS transistors," IEEE J. Solid-State Circuit, vol. SC-15, no. 4, pp. 636-643, Aug. 1980.
14. L. W. Nagel and D. O. Pederson, "Simulation program with integrated circuit emphasis," in Proc. 16th Midwest Symp. Circuit Theory, Waterloo, ON, Canada, Apr. 1973, p. 23.
15. H. C. Pao and C. T. Sah, "Effects of diffusion current on characteristics of metal-oxide (insulator)-semiconductor transistor (MOST)," Solid State Electron., vol. 9, no. 10, pp. 927-937, Oct. 1966.
16. F. H. Gaensslen and R. C. Jaeger, "Temperature dependent threshold behavior of depletion mode MOSFETs," Solid State Electron., vol. 22, no. 4, pp. 423-130, Apr. 1979.
17. J. R. Brews, "A charge-sheet model of the MOSFET," Solid State Electron., vol. 21, no. 2, pp. 345-355, Feb. 1978.
18. G. Gildenblat, X. Li, H. Wang, W. Wu, R. van Langevelde, A. J. Scholten, G. D. J. Smit, and D. B. M. Klaassen, "Introduction to PSP MOSFET model," in Proc. Tech. WCM, 2005, pp. 19-24.
19. R. Rios, S. Mudanai, W.-K. Shih, and P. Packan, "An efficient surface potential solution algorithm for compact MOSFET models," in IEDM Tech. Dig., 2004, pp. 755-758.
20. M. Miura-Mattausch, M. Suetake, H. J. Mattausch, S. Kumashiro, N. Shigyo, S. Odanaka, and N. Nakayama, "Physical modeling of the reverse-short-channel effect for circuit simulation," IEEE Trans. Electron Devices, vol. 48, no. 10, pp. 2449-2452, Oct. 2001.
21. H. J. Mattausch, M. Suetake, D. Kitamaru, M. Miura-Mattausch, S. Kumashiro, N. Shigyo, S. Odanaka, and N. Nakayama, "Simple nondestructive extraction of the vertical channel-impurity profile of small-size metal-oxide-semiconductor field-effect transistors," Appl. Phys. Lett., vol. 80, no. 16, pp. 2994-2996, Apr. 2002.
22. D. Buss, "Device issues in the integration of analog/RF functions in deep submicron digital CMOS," in IEDM Tech. Dig., 1999, pp. 423-426.
23. th model of pocket-implant MOSFETs for circuit simulation," in Proc. SISPAD, 2001, pp. 392-395.
24. H. Ueno, D. Kitamaru, K. Morikawa, M. Tanaka, M. Miura-Mattausch, H. J. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita, and N. Nakayama, "Impurity-profile-based threshold-voltage model of pocket-implanted MOSFETs for circuit simulation," IEEE Trans. Electron Devices, vol. 49, no. 10, pp. 1783-1789, Oct. 2002.
25. T. Ando, A. B. Fowler, and F. Stem, "Electronic properties of two-dimensional systems," Rev. Mod. Phys., vol. 54, no. 2, pp. 437-672, Apr. 1982.
26. Y. Matsumoto and Y. Uemura, "Scattering mechanism and low temperature mobility of MOS inversion layers," Jpn. J. Appl. Phys., vol. 2, Suppl. 2, pp. 367-370, 1974.
27. A. G. Savinis and J. T. Clemens, "Characterization of the electron mobility in the inverted 〈100〉 Si surface," in IEDM Tech. Dig., 1979, pp. 18-21.
28. S. Takagi, M. Iwase, and A. Toriumi, "On the universality of inversion-layer mobility in n- and p-channel MOSFETs," in IEDM Tech. Dig., 1988, pp. 398-401.
29. S. Matsumoto, K. Hisamitsu, M. Tanaka, H. Ueno, M. Miura-Mattaucsh, H. J. Mattausch, S. Kumashiro, T. Yamaguchi, S. Odanaka, and N. Nakayama, "Validity of the mobility universality for scaled metal-oxide-semiconductor field-effect transistors down to 100 nm gate length," J. Appl. Phys., vol. 92, no. 9, pp. 5228-5232, Nov. 2002.
30. D. M. Caughey and R. E. Thomas, "Carrier mobilities in silicon empirically related to doping and field," Proc. Inst. Etectr. Eng., vol. 55, no. 12, pp. 2192-2193, Dec. 1967.
31. M. Tanaka, H. Ueno, O. Matsushima, and M. Miura-Mattausch, "High-electric-field electron transport at silicon/silicon-dioxide interface inversion layer," Jpn. J. Appl. Phys., vol. 42, no. 3B, pp. L280-L282, Mar. 2003.
32. Compact Model Council. [Online]. Available: http://www.eigroup.org/cmc/ next_gen_cmos/phase3/HiSIM-2_full-chrf_examples.pdf
33. N. Sadachika, Y. Uetsuji, D. Kitamaru, H. J. Mattausch, M. Miura-Mattausch, L. Weiss, U. Feldmann, and S. Baba, "Fully-depleted SOI-MOSFET model for circuit simulation and its application to 1/f noise analysis," in Proc. Simul. Semicond. Processes and Devices, 2004, pp. 251-254.
34. B. Razavi, "CMOS technology characterization for analog and RF," IEEE J. Solid-State Circuits, vol. 34, p. 268, 1999.
35. D. Navarro, N. Nakayama, K. Machida, Y. Takeda, S. Chiba, H. Ueno, H. J. Mattausch, and M. Miura-Mattausch, "Modeling for carrier transport dynamics at GHz-frequencies for RF circuit-simulation," in Proc. SISPAD, 2004, pp. 259-262.
36. Y. Takeda, D. Navarro, S. Chiba, M. Miura-Mattausch, H. J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Kumashiro, and S. Miyamoto, "MOSFET harmonic distortion analysis up to the non-quasi-static frequency regime," in Proc. CICC, 2005, pp. 827-830.
37. A. van der Ziel, Noise in Solid State Devices and Circuit. New York: Wiley, 1986.
38. S. Christensson, L. Lundstorm, and C. Svensson, "Low frequency noise in MOS transistors-I Theory," Solid State Electron., vol. 11, no. 9, pp. 797-812, Sep. 1968.
39. S. Matsumoto, H. Ueno, S. Hosokawa, T. Kitamura, M. Miura-Mattausch, H. J. Mattausch, T. Ohguro, S. Kumashiro, T. Yamaguchi, K. Yamashita, and N. Nakayama, "1/f-noise characteristics in 100 nm-MOSFETs and its modeling for circuit simulation," IEICE Trans. Electron., vol. E88-C, no. 2, pp. 247-254, 2005.
40. H. Nyquist, "Thermal agitation of electric charge in conductors," Phys. Rev., vol. 32, no. 1, pp. 110-113, Jul. 1928.
41. S. Hosokawa, D. Navarro, M. Miura-Mattausch, H. J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Kumashiro, and S. Miyamoto, "Gate-length and drain-voltage dependence of thermal drain noise in advanced metal-oxide- semiconductor-field-effect transistors," Appl. Phys. Lett., vol. 87, no. 9, p. 092104, 2005.
42. S. Hosokawa, Y. Shiraga, H. Ueno, M. Miura-Mattausch, H. J. Mattausch, T. Ohguro, S. Kumashiro, M. Taguchi, H. Masuda, and S. Miyamoto, "Origin of enhanced thermal noise for 100 nm-MOSFETs," in Proc. Ext. Abstr. SSDM, 2003, pp. 20-21.
43. T. Warabino, M. Miyake, N. Sadachika, D. Navarro, Y. Takeda, G. Suzuki, T. Ezaki, M. Miura-Mattausch, H. J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Kumashiro, and S. Miyamoto, "Analysis and compact modeling of MOSFET high-frequency noise," in Proc. SISPAD, Sep. "2006, to be published.
44. A. J. Scholten, L. F. Tiemeijer, P. W. H. de Vreede, and D. B. M. Klaassen, "A large signal non-quasi-static MOS model for RF circuit simulation," in IEDM Tech. Dig., 1999, pp. 163-166.
45. T. Okagaki, M. Tanaka, H. Ueno, and M. Miura-Mattausch, "Importance of ballistic carriers for the dynamic response in sub-100 nm MOSFETs," IEEE Electron Device Lett., vol. 23, no. 3, pp. 154-156, Mar. 2002.
46. N. Nakayama, D. Navarro, M. Tanaka, H. Ueno, M. Miura-Mattausch, H. J. Mattausch, T. Ohguro, S. Kumashiro, M. Taguchi, T. Kage, and S. Miyamoto, "Non-quasi-static model for MOSFET based on carrier-transit delay," Electron. Lett., vol. 40, no. 4, pp. 276-278, Feb. 2004.
47. D. Navarro, N. Nakayama, K. Machida, Y. Takeda, M. Miura-Mattausch, H. J. Mattausch, T. Ohguro, T. lizuka, M. Taguchi, and S. Miyamoto, "A carrier transit time delay-based non-quasi-static MOSFET model for RF circuit simulation," in Proc. IWCM, 2005, pp. 23-27.
48. D. Navarro, Y. Takeda, M. Miyake, N. Nakayama, K. Machida, T. Ezaki, H. J. Mattausch, and M. Miura-Mattausch, "A carrier-transit-delay-based non-quasi-static MOSFET model for circuit simulation and its application to harmonic distortion analysis," IEEE Trans. Electron Devices, to be published.
49. Y. P. Tsividis, Operation and Modeling of the MOS Transistor. New York: McGraw-Hill, 1999.
50. J. J. Paulos and D. A. Antoniadis, "Limitations of quasi-static capacitance models for MOS transistor," IEEE Electron Device Lett., vol. EDL-4, no. 7, pp. 221-224, Jul. 1983.
51. Y. Niitsu, "Simple small-signal model for 3-port MOS transistors," IEICE Trans. Electron., vol. E79-C, no. 12, pp. 1760-1765, 1996.
52. S. Jinbou, H. Ueno, H. Kawano, K. Morikawa, N. Nakayama, M. Miura-Mattausch, and H. J. Mattausch, "Analysis of non-quasistatic contribution to small-signal response for deep sub-fim MOSFET technologies," in Proc. Ext. Abstr. SSDM, 2002, pp. 26-27.
53. H. Ueno, S. Jinbou, H. Kawano, K. Morikawa, N. Nakayama, M. Miura-Mattausch, and H. J. Mattausch, "Drift-diffusion-based modeling of the non-quasistatic small-signal response for RF-MOSFET applications," in Proc. SISPAD, 2002, pp. 71-74.
54. C. C. Enz and Y. Cheng, "MOS transistor modeling for RF IC design," IEEE J. Solid-State Circuits, vol. 35, no. 2, pp. 186-201, Feb. 2000.
55. K. Machida, D. Navarro, M. Miyake, R. Inagaki, N. Sadachika, T. Ezaki, H. J. Mattausch, and M. Miura-Mattausch, "Efficient non-quasi-static MOSFET model for both time-domain and frequency-domain analysis," in Proc. Silicon Monolithic Integr. Circuits RF Syst., Jan. 2006, pp. 73-76.
56. D. Miyawaki, S. Matsumoto, H. J. Mattausch, S. Ooshiro, M. Suetake, M. Miura-Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita, and N. Nakayama, "Correlation method of circuit-performance and technology fluctuations for improved design reliability," in Proc. Asia South Pacific Data Autom. Conf., 2001, pp. 39-44.
57. S. Matsumoto, H. J. Mattausch, S. Ooshiro, Y. Tatsumi, M. Miura-Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita, and N. Nakayama, "Test-circuit-based extraction of inter- and intra-chip MOSFET-performance variations for analog-design reliability," in Proc. Custom Integr. Circuits Conf., 2001, pp. 357-360.
58. T. Mizoguchi, H. J. Mattausch, H. Ueno, D. Kitamaru, K. Hisamitsu, M. Miura-Mattausch, S. Itoh, and K. Morikawa, "Extraction of inter-and intra-chip device-parameter variations with a differential-amplifier-stage test circuit," in Proc. SASIMI, 2003, pp. 76-82.