Test-circuit-based extraction of inter- and intra-chip MOSFET-performance variations for analog-design reliability

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2001, Pages 357-360

  Matsumoto, S ^a   Mattausch, H J ^a   Ooshiro, S ^a   Tatsumi, Y ^a   Miura Mattausch, M ^a   Kumashiro, S ^b   Yamaguchi, T ^b   Yamashita, K ^b   Nakayama, N ^b  

^a HIROSHIMA UNIVERSITY   (Japan)

^b SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIFFERENTIAL AMPLIFIERS; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; MATHEMATICAL MODELS;

FEEDBACK COUPLING; INTERCHIP VARIATION; INTRACHIP VARIATION;

MOSFET DEVICES;

EID: 0034822325     PISSN: 08865930     EISSN: None     Source Type: Journal    
DOI: 10.1109/CICC.2001.929801     Document Type: Article

References (7)

1. Reducting cross-coupling among interconnect wires in deep-submicron datapath design
2. Unified complete MOSFET model for analysis of degital and analog circuits
3. Analysis and decomposition of spacial variation in integrated circuit processes and devices
4. Within-chip variability analysis
5. Optimization of advanced MOS technologies for narrow distribution of circuit performance
6. Characterization and modeling of mismatch in MOS transistors for precision analog design
7. HiSIM: A drift-diffusion-based advanced MOSFET model for circuit simulation with easy parameter extraction