Technology-circuit co-design in width-quantized quasi-planar double-gate SRAM

2005 International Conference on Integrated Circuit Design and Technology, ICICDT

Volumn , Issue , 2005, Pages 155-160

  Ananthan, Hari ^a   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC RANDOM ACCESS STORAGE; FIELD EFFECT TRANSISTORS; LEAKAGE CURRENTS; STATIC RANDOM ACCESS STORAGE;

DOUBLE-GATE TECHNOLOGY; GATE LEAKAGE; SHORT-CHANNEL EFFECTS; SOURCE-DRAIN LEAKAGE;

INTEGRATED CIRCUIT LAYOUT;

EID: 25844486080     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/icicdt.2005.1502618     Document Type: Conference Paper

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