-
1
-
-
85056911965
-
"Monte Carlo simulation of a 30 nm dual-gate MOSFET: How short can Si go?
-
1992, pp. 553-556.
-
D. J. Frank, S. E. Laux, and M. V. Fischetti, "Monte Carlo simulation of a 30 nm dual-gate MOSFET: How short can Si go?," in IEDM Tech. Dig., Dec. 1992, pp. 553-556.
-
" in IEDM Tech. Dig., Dec.
-
-
Frank, D.J.1
Laux, S.E.2
Fischetti, M.V.3
-
2
-
-
0032306225
-
"Simulation-based assessment of 50 nm double-gate CMOS performance
-
1998, pp. 107-108.
-
J. G. Possum and Y. Chong, "Simulation-based assessment of 50 nm double-gate CMOS performance," in Proc. IEEE Int. SOI Conf., Oct. 1998, pp. 107-108.
-
" in Proc. IEEE Int. SOI Conf., Oct.
-
-
Possum, J.G.1
Chong, Y.2
-
3
-
-
0029403527
-
"Analytical models for n+-p+ double-gate SOI MOSFET's
-
vol. 42, pp. 1940-1948, Nov. 1995.
-
K. Suzuki and T. Sugii, "Analytical models for n+-p+ double-gate SOI MOSFET's," IEEE Trans. Electron Devices, vol. 42, pp. 1940-1948, Nov. 1995.
-
" IEEE Trans. Electron Devices
-
-
Suzuki, K.1
Sugii, T.2
-
4
-
-
33747204357
-
"Modeling and design of deep-submicron fully depleted silicon-on-insulator complementary metal-oxide-semiconductor for lowvoltage integrated circuit applications
-
P. C. Yeh, "Modeling and design of deep-submicron fully depleted silicon-on-insulator complementary metal-oxide-semiconductor for lowvoltage integrated circuit applications," Ph.D. dissertation, Univ. Florida, Gaines ville, 1996.
-
" Ph.D. Dissertation, Univ. Florida, Gaines Ville, 1996.
-
-
Yeh, P.C.1
-
5
-
-
84886447996
-
"Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel
-
1997, pp. 42730.
-
H. P. Wong, K. K. Chan, and Y. Taur, "Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel," in IEDM Tech. Dig., Dec. 1997, pp. 42730.
-
" in IEDM Tech. Dig., Dec.
-
-
Wong, H.P.1
Chan, K.K.2
Taur, Y.3
-
6
-
-
0023454470
-
"Subbreakdown drain leakage current in MOSFET's
-
8, pp. 515-517, Nov. 1987.
-
J. Chen, T. Y. Chan, I. C. Chen, P. K. Ko, and C. Hu, "Subbreakdown drain leakage current in MOSFET's," IEEE Electron Device Lett., vol. EDL-8, pp. 515-517, Nov. 1987.
-
" IEEE Electron Device Lett., Vol. EDL
-
-
Chen, J.1
Chan, T.Y.2
Chen, I.C.3
Ko, P.K.4
Hu, C.5
-
7
-
-
0026954430
-
"The enhancement of gateinduced-drain-leakage (GIDL) current in short-channel SOI MOSFET and its application in measuring lateral bipolar current gain β"
-
vol. 13, pp. 572-574, Nov. 1992.
-
J. Chen, F. Assaderaghi, P. K. Ko, and C. Hu, "The enhancement of gateinduced-drain-leakage (GIDL) current in short-channel SOI MOSFET and its application in measuring lateral bipolar current gain β" IEEE Electron Device Lett., vol. 13, pp. 572-574, Nov. 1992.
-
IEEE Electron Device Lett.
-
-
Chen, J.1
Assaderaghi, F.2
Ko, P.K.3
Hu, C.4
-
8
-
-
33747169632
-
"A preliminary simulation-based assessment of double-gate CMOS devices and circuits
-
Y. Chong, "A preliminary simulation-based assessment of double-gate CMOS devices and circuits," M.S. thesis, Univ. Florida, Gainesville, 1998.
-
" M.S. Thesis, Univ. Florida, Gainesville, 1998.
-
-
Chong, Y.1
-
9
-
-
33747193572
-
"UFSOI model parameter evaluation: Process-based calibration
-
M.-H. Chiang and J. G. Possum, "UFSOI model parameter evaluation: Process-based calibration," SOI Group Rep., Univ. Florida, Gainesville, Nov. 1998.
-
" SOI Group Rep., Univ. Florida, Gainesville, Nov. 1998.
-
-
Chiang, M.-H.1
Possum, J.G.2
-
10
-
-
0031078966
-
"Electron and hole quantization and their impact on deep submicron silicon p- And n-MOSFET characteristics
-
vol. 44, pp. 297-303, Feb. 1997.
-
S. Jallepalli, J. Bude, W.-K. Shih, M. R. Pinto, C. M. Maziar, and A. F. Tasch, Jr., "Electron and hole quantization and their impact on deep submicron silicon p- and n-MOSFET characteristics," IEEE Trans. Electron Devices, vol. 44, pp. 297-303, Feb. 1997.
-
" IEEE Trans. Electron Devices
-
-
Jallepalli, S.1
Bude, J.2
Shih, W.-K.3
Pinto, M.R.4
Maziar, C.M.5
Tasch, A.F.6
Jr7
-
11
-
-
84886448163
-
"A 0.10 mm gate length CMOS technology with 30 A gate dielectric for 1.0-1.5 v applications
-
1997, pp. 223226.
-
M. Rodder, M. Hanratty, D. Rogers, T. Laaksonen, J. C. Hu, S. Murtaza, C. P. Chao, S. Hattangady, S. Aur, A. Amerasekera, and I. C. Chen, "A 0.10 mm gate length CMOS technology with 30 A gate dielectric for 1.0-1.5 V applications," in IEDM Tech. Dig., Dec. 1997, pp. 223226.
-
" in IEDM Tech. Dig., Dec.
-
-
Rodder, M.1
Hanratty, M.2
Rogers, D.3
Laaksonen, T.4
Hu, J.C.5
Murtaza, S.6
Chao, C.P.7
Hattangady, S.8
Aur, S.9
Amerasekera, A.10
Chen, I.C.11
-
12
-
-
0030150941
-
"Compact nonlocal modeling of impact ionization in SOI MOSFET's for optimal CMOS device/circuit design
-
vol. 39, pp. 661-668, May 1996.
-
S. Krishnan and J. G. Possum, "Compact nonlocal modeling of impact ionization in SOI MOSFET's for optimal CMOS device/circuit design," Solid-State Electron., vol. 39, pp. 661-668, May 1996.
-
" Solid-State Electron.
-
-
Krishnan, S.1
Possum, J.G.2
|