Skewed CMOS: Noise-tolerant high-performance low-power static circuit family

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 10, Issue 4, 2002, Pages 469-476

  Solomatnikov, Alexandre ^a   Somasekhar, Dinesh ^b   Sirisantana, Naran ^c   Roy, Kaushik ^c  

^a Stanford University   (United States)

^b INTEL CORPORATION   (United States)

^c Purdue University   (United States)

Author keywords

Clocks; CMOS digital integrated circuits; Design; Electromagnetic coupling; Integrated circuit noise; Methodology; Synchronization

Indexed keywords

DELAY CIRCUITS; DIGITAL INTEGRATED CIRCUITS; ELECTRIC CLOCKS; FITS AND TOLERANCES; LOGIC CIRCUITS; MULTIPLYING CIRCUITS; POWER CONTROL; SPURIOUS SIGNAL NOISE; VOLTAGE CONTROL; WAVEGUIDE COUPLERS;

DOMINO LOGIC; DYNAMIC NOISE MARGIN; ELECTROMAGNETIC COUPLING; INTEGRATED CIRCUIT NOISE; LOW POWER STATIC CIRCUIT; SKEWED LOGIC CIRCUITS;

CMOS INTEGRATED CIRCUITS;

EID: 0036705162     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2002.800519     Document Type: Article

References (14)

1. R. H. Krambeck et al., "High-speed compact circuits with CMOS," IEEE J. Solid-State Circuits, vol. SSC-17, pp. 614-619, June 1982.
2. N. F. Goncalves and H. J. Mari, "NORA: A race-free dynamic CMOS technique for pipelined logic structure," IEEE J. Solid-State Circuits, vol. SSC-18, pp. 261-266, June 1983.
3. D. Somasekhar, "Power and Dynamic Noise Considerations in High Performance CMOS VLSI Design," Ph.D., Purdue University, West Lafayette, IN, 1999.
4. t technology," in Proc. IEEE Int. Symp. Low Power Electronics and Design, San Diego, CA, June 1999, pp. 151-155.
5. D. W. Dobberpuhl et al., "200-MHz 64-bit dual-issue CMOS microprocessor," Digital Tech. J., vol. 4, no. 4, pp. 1-19, 1992.
6. F. Murabayashi et al., "2.5 V CMOS circuit design technique for a 200 MHz superscalar RISC processor," IEEE J. Solid-State Circuits, vol. 31, pp. 972-980, July 1996.
7. H. Yamada et al., "A 13.3 ns double-precision floating-point ALU and multiplier," in Proc. IEEE Int. Conf. Computer Design: VLSI in Computers and Processors, Austin, TX, Oct. 1995.
8. D. Harris and M. Horowitz, "Skew-tolerant domino circuits," IEEE J. Solid-State Circuits, vol. 32, pp. 1702-1710, Nov. 1997.
9. A. Alvandpour, P. Larsson-Edefors, and C. Svensson, "Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuits," in Proc. IEEE Int. Symp. Low Power Electronics and Design, Monterey, CA, Aug. 1998, pp. 245-249.
10. D. Somasekhar, S. H. Choi, K. Roy, Y. Ye, and V. De, "Dynamic noise analysis in precharge-evaluate circuits," in Proc. Design Automation Conf.'00, Anaheim, CA, June 2000, pp. 243-246.
11. A. Solomatnikov, D. Somasekhar, and K. Roy, "Skewed CMOS: Noise-immune high-performance low-power static circuit family," in Proc. Eur. Solid-State Circuits Conf. (ESSCIRC'00), Stockholm, Sweden, Sept. 2000, pp. 424-427.
12. T. Ghani, K. Mistry, P. Packans, S. Thompson, M. Stettler, S. Tyagi, and M. Bohr, "Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors," in Proc. 2000 Symp. VLSI Technology Dig. Tech. Papers, Honolulu, HI, June 2000, pp. 174-175.
13. D. Harris, Skew-Tolerant Circuit Design. New York: Morgan Kaufmann, 2000.
14. M. Bohr, "MOS transistors: Scaling and performance trends," Semiconductor Int., vol. 18, no. 6, p. 75, 76, 78, 80, June 1995.