Nanoscale CMOS Circuit Leakage Power Reduction by Double-Gate Device

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn 2004-January, Issue January, 2004, Pages 102-107

  Kim, Keunwoo ^a   Das, Koushik K ^a   Joshi, Rajiv V ^a   Chuang, Ching Te ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Double gate device; Leakage power; Short channel effect

Indexed keywords

CMOS INTEGRATED CIRCUITS; DESIGN; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT DESIGN; LOW POWER ELECTRONICS; POWER ELECTRONICS;

DOUBLE-GATE DEVICE; DOUBLE-GATE TECHNOLOGY; HIGH PERFORMANCE APPLICATIONS; LEAKAGE POWER; LEAKAGE POWER REDUCTION; LOW POWER APPLICATION; SHORT-CHANNEL EFFECT; TWO-DIMENSIONAL SIMULATIONS;

LEAKAGE CURRENTS;

EID: 84932110532     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/LPE.2004.240810     Document Type: Conference Paper

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