Hf-based high-k dielectrics: Process development, performance characterization, and reliability

Synthesis Lectures on Solid State Materials and Devices

Volumn 1, Issue , 2006, Pages 1-92

  Kim, Young Hee ^a   Lee, Jack C ^b  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

Dynamic reliability; HfO 2; High k dielectrics; Interface engineering; Mobility; MOSFET; Soft breakdown; TDDB; Weibull slope

Indexed keywords

DYNAMIC RELIABILITY; HIGH K DIELECTRICS; INTERFACE ENGINEERING; SOFT BREAKDOWN; WEIBULL SLOPES;

INTERFACES (MATERIALS); MOSFET DEVICES; RELIABILITY THEORY; STATISTICAL METHODS;

DIELECTRIC MATERIALS;

EID: 33751101389     PISSN: 19321260     EISSN: 19321724     Source Type: Book Series    
DOI: 10.2200/S00005ED1V01Y200508SSM001     Document Type: Article

References (34)

1. T.-S. Chen, D. Hadad, V. Valu, V. Jiang, S.-H. Kuah, P. C. McIntyre, S. R. Summerfelt, J. M. Anthony, and J. C. Lee, "Ir-electroded BST thin film capacitors for 1 giga-bit DRAM application," in IEEE International Electron Devices Meeting, 1996, pp. 679-682.
2. D. Barlage, R. Arghavani, G. Deway, M. Doczy, B. Doyle, J. Kavalieros, A. Murthy, B. Roberds, P. Stokley, and R. Chau, "High-frequency response of 100 nm integrated CMOS transistors with high-k gate dielectrics," in IEEE International Electron Devices Meeting, 2001, pp. 231-234.
3. 2 films from organo-hafnium compounds," Thin Solid Films, Vol. 41, pp. 247-259, 1997, doi:10.1016/0040-6090(77)90312-1
4. B. Cheng, M. Cao, R. Rao, A. Inani, P. V. Voorde, W. M. Greene, J. M. C. Stork, Z. Yu, P. M. Zeitzoff, and J. C. S. Woo, "The impact of high-k gate dielectrics and metal gate electrodes on sub-100 nm MOSFET's," IEEE Trans. Electron Devices, Vol. 46, pp. 1537-1544, 1999, doi:10.1109/16.7725081
5. A. Kumar, T. H. Ning, M. V. Fischetti, and E. Gusev, "Hot-carrier charge trapping and reliability in high-k dielectrics," Tech. Dig. VLSISymp., pp. 152-153, 2002.
6. 2 gate dielectric prepared by low temperature oxidation of ZrN," Tech. Dig. IEDM, pp. 459-462, 2001.
7. 2 and Zr silicate gate dielectrics," Tech. Dig. IEDM, pp. 27-30, 2000.
8. 2 high-k dielectrics," Tech. Dig. IEDM, pp. 35-38, 2000.
9. B. H. Lee, R. Choi, L. G. Kang, S. Gopalan, R. Nieh, K. Onishi, Y. J. Jeon, W. J. Qi, C. S. Kang, and J. C. Lee, "Characteristics of TaN gate MOSFET with ultrathin hafnium oxide (8 Å-12 Å)," Tech. Dig. IEDM, p. 39, 2000.
10. J. Robertson, "Band offsets of wide-band-gap oxides and implications for future electronic devices," J. Vacuum Sci. Technol. B, Vol. 18, pp. 1785-1791, 2000. doi:10.1116/1.591472
11. 2 gate dielectric MOSFETs using deuterium anneal," Tech. Dig. IEDM, pp. 613-616, 2002.
12. 2 MOSFET performance," Tech. Dig. Int. Symp. VLSI, pp. 22-23, 2002.
13. H. R. Huff, A. Hou, C. Lim, Y. Kim, J. Barnett, G. Bersuker, G. A. Brown, C. D. Young, P. M. Zeitzoff, J. Gutt, P. Lysaght, M. I. Gardner, and R. W. Murto, "Integration of high-k gate stacks into planar, scaled CMOS integrated circuits," in Conf. Nano and Giga Challenges in Microelectronics, pp. 1-18, 2002.
14. W.-D. Kim, J.-H. Joo, Y.-K. Jeong, S.-J. Won, S.-Y. Park, S.-C. Lee, C.-Y. Yoo, S.-T. Kim, and J.-T. Moon, "Development of CVD-Ru/Ta,O,/CVD-Ru capacitor with concave structure for multigigabit-scale DRAM generation," Tech. Dig. IEDM, pp. 12.1.1-12.1.4, 2002.
15. 3 trench capacitor DRAM for sub-100 nm technology, " Tech. Dig. IEDM, pp. 839-842, 2002.
16. C. B. Oh, H. S. Kang, H. J. Ryu, M. H. Oh, H. S. Jung, Y. S. Kim, J. H. He, N. I. Lee, K. H. Cho, D. H. Lee, T. H. Yang, I. S. Cho, H. K. Kang, Y. W. Kim, and K. P. Suh, "Manufacturable embedded CMOS 6T-SRAM technology with high-k gate dielectric device for system-on-chip applications," Tech. Dig. IEDM, pp. 423-426, 2002.
17. Y. Matsui, M. Hiratani, I. Asano, and S. Kimura, "Niobia-stabilized tantalum pentoxide (NST)-Novel high-j dielectrics for low-temperature process of MIM capacitors," Tech. Dig. IEDM, pp. 225-228, 2002.
18. L. Manchanda, M. L. Green, R. B. van Dover, M. D. Morris, A. Kerber, Y. Hu, J.-P. Han, P. J. Silverman, T. W. Sorsch, G. Weber, V. Donnelly, K. Pelhos, F. Klemens, N. A. Ciampa, A. Kornblit, Y. O. Kim, J. E. Bower, D. Barr, E. Ferry, D. Jacobson, J. Eng, B. Busch, and H. Schulte, "Si-doped aluminates for high temperature metal-gate CMOS: Zr-Al-Si-O, a novel gate dielectric for low power applications," Tech. Dig. IEDM, pp. 23-26, 2000.
19. T. Sugizald, M. Kobayashi, M. Ishidao, H. Minakata, M. Yamaguchi, Y. Tamura, Y. Sugiyarna, T. Nakanishi, and H. Tanaka, "Novel multi-bit sonos type flash memory using a high-k charge trapping layer," Tech. Dig. Int. Symp. VLSI., pp. 27-28, 2003.
20. Y. L. Tu, H. L. Lin, L. L. Chao, D. Wu, C. S. Tsai, C. Wang, C. F. Huang, C. H. Lin, and J. Sun, "Characterization and comparison of high-k metal-insulator-metal (mim) capacitors in 0.13 um Cu BEOL for mixed-mode and rf applications," Tech. Dig. Int. Symp. VLSI., pp. 79-80, 2003.
21. 2 high-k tunneling dielectric," Tech. Dig. Int. Symp. VLSI., pp. 33-34, 2003.
22. 2 under dynamic and constant voltage stress," Tech. Dig. IEDM, pp. 629-632, 2002.
23. T. Kauerauf, R. Degraeve, E. Cartier, C. Soens, and G. Groesenenken, "Low Weibull slope of breakdown distributions in high-k layers," IEEE Electron Device Lett., Vol. 23, pp. 215-217, 2002. doi:10.1109/55.9922843
24. 2 gate dielectrics," IEEE Electron Device Lett., Vol. 23, pp. 594-596, 2002. doi:10.1109/LED.2002.1004214
25. 2 gate dielectrics," IEEE Electron Device Lett., pp. 40-42, 2003.
26. 2 high-k dielectrics," Tech. Dig. IEDM, pp. 35-38, 2000.
27. J. Lee, H. Zhong, Y.-S. Suh, G. Heuss, J. Gurganus, B. Chen, and V. Misra, "Tunable work function dual metal gate technology for bulk and non-bulk CMOS," Tech. Dig. IEDM, pp. 359-362, 2002.
28. J. McPherson, J. Kim, A. Shanware, H. Mogul, and J. Rodriguez, "Proposed universal relationship between dielectric breakdown and dielectric constant," Tech. Dig. IEDM, pp. 634-637, 2002.
29. R. Degraeve, G. Groeseneken, R. Bellens, M. Depas, and H. E. Macs, "A consistent model for the thickness dependence of intrinsic breakdown in ultra-thin oxides," Tech. Dig. IEDM, pp. 863-866, 1995.
30. M. Houssa, T. Nigam, P. W. Mertens, and M. M. Heyns "Model for the current-voltage characteristics of ultra thin gate oxide after soft breakdown," J. App. Phys., Vol. 84, pp. 4351-4355, 1998. doi:10.1063/1.368654
31. J. H. Stathis and D. J. DiMaria, "Reliability projection for ultra-thin oxides at low voltage," Tech. Dig. IEDM, pp. 167-170, 1998.
32. J. H. Stathis, "Physical and predictive models of ultra thin oxide reliability in CMOS devices and circuits," IRPS proceeding of IEEE international reliability physics symposium, pp. 132-149, 2001.
33. 2 films," Thin Solid Films, Vol. 185, pp. 347-362, 1990. doi:10.1016/0040-6090(90)90098-X
34. J. H. Stathis, "Percolation models for gate oxide breakdown," J. Appl. Phys., Vol. 86, pp. 5757-5766, 1999. doi:10.1063/1.371590