A 60 mW per Lane, 4 × 23-Gb/s 2 7-1 PRBS generator

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 10, 2006, Pages 2198-2208

  Laskin, Ekaterina ^a,b   Voinigescu, Sorin P ^a,b  

^a IEEE   (Canada)

^b UNIVERSITY OF TORONTO   (Canada)

Author keywords

Current mode logic; OCTC; Pseudo random bit sequence generator; SiGe BiCMOS; Technology scaling

Indexed keywords

CURRENT-MODE LOGIC; PSEUDO-RANDOM BIT SEQUENCE GENERATORS; SIGE BICMOS; TECHNOLOGY SCALING;

CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK TOPOLOGY; SPEED CONTROL;

ELECTRIC GENERATORS;

EID: 33749524068     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.878112     Document Type: Conference Paper

References (33)

1. M. G. Chen and J. K. Notthoff, "A 3.3 V, 21 Gb/s PRBS generator in AlGaAs/GaAs HBT technology," IEEE J. Solid-State Circuits, vol. 35, no. 9, pp. 1266-1270, Sep. 2000.
2. H. Veenstra, "1-58 Gb/s PRES generator with <1.1 ps RMS jitter in InP technology," in Proc. ESSCIRC, Sep. 2004, pp. 359-362.
3. M. Bussmann, U. Langmann, W. J. Hillery, and W. W. Brown. "PRBS generation and error detection above 10 Gb/s using a monolithic Si bipolar IC," J. Lightw. Technol., vol. 12, no. 2, pp. 353-360, Feb. 1994.
4. F. Schumann and J. Böck, "Silicon bipolar 1C for PRBS testing generates adjustable bit rates up to 25 Gbit/s," Election. Lett., vol. 33, pp. 2022-2023, Nov. 1997.
5. O. Kromat, U. Langmann, G. Hanke, and W. J. Hillery. "A 10-Gb/s silicon bipolar IC for PRBS testing," IEEE J. Solid-State Circuits, vol. 33, no. 1, pp. 76-85, Jan. 1998.
6. H. Knapp, M. Wurzer, T. F. Meister, J. Bock, and K. Aufinger, "40 Gbit/s 27- 1 PRBS generator IC in SiGe bipolar technology," in Proc. Bipolar/BiCMOS Circuits and Technology Meeting, Sep. 2002, pp. 124-127.
7. 11-1 PRBS generators in SiGe bipolar technology," IEEE J. Solid-State Circuits, vol. 40, no. 10, pp. 2118-2125, Oct. 2005.
8. 7-1 SiGe PRBS generator IC up to 86 Gbit/s," in Proc. Gallium Arsenide Applications Symp., Amsterdam, The Netherlands, Oct. 2004, pp. 335-338.
9. R. Malasani, C. Bourde, and G. Gutierrez, "A SiGe 10-Gb/s multipattern bit error rate tester," in Proc. IEEE Radio Frequency Integrated Circuits (RFIC) Symp., Jun. 2003, pp. 321-324.
10. S. Kim, M. Kapur, M. Meghelli, A. Rylyakov, Y. Kwark, and D. Friedman, "45-Gb/s SiGe BiCMOS PRBS generator and PRBS checker," in Proc. IEEE Custom Integrated Circuits Conference (CICC), Sep. 2003, pp. 313-316.
11. 7-1 PRBS generator in SiGe using a low-voltage logic family," in IEEE ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2005, pp. 340-341.
12. 7-1 pseudo random bit sequence generator IC in 120 nm bulk CMOS," in Proc. Symp. Integrated Circuits and Systems Design (SBCCI), Sep. 2004, pp. 233-236.
13. 31-1 PRBS generator in SiGe BiCMOS technology," in IEEE ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2005, pp. 342-345.
14. 31 -1 pseudorandom binary sequence generator in SiGe BiCMOS technology," in IEEE J. Solid-State Circuits, Dec. 2005, vol. 40, no. 12, pp. 2735-2745.
15. W. McFarland, K. Springer, and C.-S. Yen, "1-Gword/s pseudorandom word generator," IEEE J. Solid-State Circuits, vol. 24, no. 6, pp. 747-751, Jun. 1989.
16. S. W. Golomb, Shift Register Sequences. San Francisco, CA: Holden-Day, 1967.
17. F. Sinnesbichler, A. Ebberg, A. Felder, and R. Weigel, "Generation of high-speed pseudorandom sequences using multiplex techniques," IEEE Trans. Microw. Theory Tech., vol. 44, no. 12, pp. 2738-2742, Dec. 1996.
18. A. N. Van-Luyn, "Shift register connections for delayed versions of m-sequences," Electron. Lett., vol. 14, pp. 713-715, Oct. 1978.
19. J. J. O'Reilly, "Series-parallel generation of m-sequences," The Radio and Electronic Engineer, vol. 45, pp. 171-176, Apr. 1975.
20. B. Razavi, Design of Integrated Circuits for Optical Communications. New York: McGraw-Hill, 2003.
21. T. O. Dickson, R. Beerkens, and S. P. Voinigescu, "A 2.5-V 45-Gb/s decision circuit using SiGe BiCMOS logic," IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 994-1003, Apr. 2005.
22. T. O. Dickson, K. H. K. Yau, T. Chalvatzis, A. Mangan, E. Laskin, R. Beerkens, P. Westergaard, M. Tazlauanu, M. Yang, and S. P. Voinigescu, "The invariance of characteristic current densities in nanoscale MOSFETs and its impact on algorithmic design methodologies and design porting of Si(Ge) (Bi)CMOS high-speed building blocks," IEEE J. Solid-State Circuits, vol. 41, no. 8, pp. 1830-1845, Aug. 2006.
23. A. S. Sedra and K. C. Smith, Microelectronic Circuits, 5th ed. New York: Oxford Press, 2004.
24. S. P. Voinigescu, T. O. Dickson, T. Chalvatzis, A. Hazneci, E. Laskin, R. Beerkens, and I. Khalid, "Algorithmic design methodologies and design porting of wireline transceiver IC building blocks between technology nodes," in Proc. IEEE Custom Integrated Circuits Conf., 2005, pp. 110-117.
25. T. E. Collins, V. Manan, and S. I. Long, "Design analysis and circuit enhancements for high-speed bipolar flip-flops," IEEE J. Solid-State Circuits, vol. 40, no. 5, pp. 1166-1174, May 2005.
26. T. O. Dickson, M.-A. LaCroix, S. Boret, D. Gloria, R. Beerkens, and S. P. Voinigescu, "30-100-GHz inductors and transformers for millimeter-wave (Bi)CMOS integrated circuits," IEEE Trans. Microw. Theory Tech., vol. 53, no. 1, pp. 123-133, Jan. 2005.
27. S. P. Voinigescu, T. Dickson, R. Beerkens, I. Khalid, and P. Westergaard, "A comparison of Si CMOS, SiGe BiCMOS, and InP HBTs technologies for high-speed and millimeter-wave ICs," in Proc. Si Monolithic Integrated Circuits in RF Systems, Atlanta, GA, 2004, pp. 111-114.
28. T. H. Lee, The Design of CMOS Radio Frequency Integrated Circuits, 2nd ed. New York: Cambridge, 2004.
29. max 0.13-μm SiGe:C BiCMOS technology," in Proc. Bipolar/BiCMOS Circuits and Technology Meeting, Sep. 2003, pp. 199-202.
30. P. Chevalier, C. Fellous, L. Rubaldo, F. Pourchon, S. Pruvost, R. Beerkens, F. Saguin, N. Zerounian, B. Barbalat, S. Lepilliet, D. Dutartre, D. Celi, I. Telliez, D. Gloria, F. Aniel, F. Danneville, and A. Chantre, "230-GHz self-aligned SiGeC HBT for optical and millimeter-wave applications," IEEE J. Solid-State Circuits, vol. 40, no. 10, pp. 2025-2034, Oct. 2005.
31. 7-1 PRBS generator," in Proc. IEEE Compound Semiconductor Integrated Circuit Symp., Oct. 2005, pp. 192-195.
32. Y. Amamiya, Y. Suzuki, J. Yamaraki, A. Fujihara, S. Tanaka, and H. Hida, "1.5-V low supply voltage 43-Gb/s delayed flip-flop circuit," in Proc. IEEE Gallium Arsenide Integrated Circuits (GaAs IC) Symp., Nov. 2003, pp. 169-172.
33. K. Kanda, D. Yamazaki, T. Yamamoto, M. Horinaka, J. Ogawa, H. Tamura, and H. Onodera, "40 Gb/s 4:1 MUX/1:4 DEMUX in 90 nm standard CMOS," in IEEE ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2005, pp. 152-153.