The invariance of characteristic current densities in nanoscale MOSFETs and its impact on algorithmic design methodologies and design porting of Si(Ge) (Bi)CMOS high-speed building blocks

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 8, 2006, Pages 1830-1844

  Dickson, Timothy O ^a,b   Yau, Kenneth H K ^a,b   Chalvatzis, Theodoras ^b   Mangan, Alain M ^b   Laskin, Ekaterina ^a,b   Beerkens, Rudy ^a,c   Westergaard, Paul ^b   Tazlauanu, Mihai ^a,d   Yang, Ming Ta ^a,e   Voinigescu, Sorin P ^a,b  

^a IEEE   (Canada)

^b UNIVERSITY OF TORONTO   (Canada)

^c STMICROELECTRONICS   (Canada)

^d Quake Technologies   (Canada)

^e TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

Characteristic current densities; F max; F t; Low noise transimpedance amplifiers; MOS CML; Nanoscale CMOS; Noise figure; Operational amplifiers; Output drivers; SiGe BiCMOS; SOI; Wave shape control

Indexed keywords

CHARACTERISTIC CURRENT DENSITIES; FMAX; FT; LOW-NOISE TRANSIMPEDANCE AMPLIFIERS; MOS-CML; NANOSCALE CMOS; NOISE FIGURENOISE FIGURE; OUTPUT DRIVERS; SIGE BICMOS; SOI;

ALGORITHMS; BANDWIDTH; GAUSSIAN NOISE (ELECTRONIC); LOGIC GATES; MICROPROCESSOR CHIPS; MOSFET DEVICES; OPERATIONAL AMPLIFIERS; SEMICONDUCTING SILICON COMPOUNDS; TRANSCEIVERS;

CURRENT DENSITY;

EID: 33746927173     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.875301     Document Type: Conference Paper

References (35)

1. S. P. Voinigescu, T. O. Dickson, T. Chalvatzis, A. Hazneci, E. Laskin, R. Beerkens, and I. Khalid, "Algorithmic design methodologies and design porting of wireline transceiver IC building blocks between technology nodes," in Proc. IEEE CICC, San Diego, CA, Sep. 2005, pp. 111-118.
2. 31-1 pseudo-random binary sequence generator in SiGe BiCMOS technology," IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2735-2745, Dec. 2005.
3. S. E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, T. Hoffman, C.-H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Z. Ma, B. Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetti, P. Nguyen, S. Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr, and Y. El-Mansy, "A 90-nm logic technology featuring strained-silicon," IEEE Trans. Electron Devices, vol. 51, no. 11, pp. 1790-1797, Nov. 2004.
4. Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices. Cambridge, U.K.: Cambridge Univ. Press, 1998, ch. 3, pp. 132-135.
5. ITRS-2003. [Online]. Available: www.itts.net/Common/2004Update/ 2004Update.htm
6. B. Jangannathan, D. Greenberg, D. I. Sanderson, J.-S. Rieh, J. Pekarik, J. O. Plouchard, and G. Freeman, "Speed and power performance comparison of state-of-the-art CMOS and SiGe RF transistors," in Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, Dig. Tech. Papers, Sep. 2004, pp. 115-118.
7. K. Kuhn, R. Basco, D. Becher, M. Hattendorf, P. Packan, I. Post, P. Vandervoorn, and I. Young, "A comparison of state-of-the-art nMOS and SiGe HBT devices for analog/mixed-signal/RF circuit applications," in Symp. VLSI Technology Dig. Tech. Papers, Jun. 2004, pp. 224-225.
8. max, 90-nm SOI CMOS SoC technology with low-power millimeter-wave digital and RF circuit capability," in Symp. VLSI Technology Dig. Tech. Papers, Jun. 2004, pp. 98-99.
9. S. P. Voinigescu, D. S. McPherson, F. Pera, S. Szilagyi, M. Tazlauanu, and H. Tran, "A comparison of silicon and III-V technology performance and building block implementations for 10 and 40 Gb/s optical networking ICs," Compound Semiconductor Integrated Circuits, Selected Topics in Electmnics and Systems, vol. 29, no. 1, pp. 27-58, 2003, World Scientific.
10. S. P. Voinigescu, T. O. Dickson, R. Beerkens, I. Khalid, and P. Westergaard, "A comparison of Si CMOS, SiGe BiCMOS, and InP HBTs technologies for high-speed and millimeter-wave ICs," in 5th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, Dig. Tech. Papers, Sep. 2004, pp. 111-114.
11. S. P. Voinigescu, S. W. Tarasewicz, T. MacElwee, and J. Ilowski, "An assessment of the state-of-the-art 0.5 μm bulk CMOS technology for RF applications," in IEDM Tech. Dig., 1995, pp. 721-724.
12. T NMOS) demonstrated on a 5 GHz LNA," in Symp. VLSI Technology Dig. Tech. Papers, Jun. 2004, pp. 100-101.
13. S. P. Voinigescu, R. Beerkens, T. O. Dickson, and T. Chalvatzis, "Design methodologies and applications of SiGe BiCMOS cascode opamps with up to 37-GHz unity gain bandwidth," in IEEE CSIC Symp. Tech. Dig., Nov. 2005, pp. 283-286.
14. G. Ng, B. Lai, P. Liu, and S. P. Voinigescu, "1 GHz OpAmp based bandpass filter," in Si Monolithic Integrated Circuits in RF Systems, Tech. Dig., Jan. 2006, pp. 369-372.
15. S. P. Voinigescu, T. O. Dickson, M. Gordon, C. Lee, T. Yao, A. Mangan, K. Tang, and K. H. K. Yau, "RF and millimeter-wave IC design in the nano-(Bi)CMOS era," in Si-Based Semiconductor Components for Radio-Frequency Integrated Circuits (RFIC), 2006, W. Z. Cai, Ed. New Delhi, India: Transworld Research Network, ISBN 81-7895-196-7.
16. M. Vertregt and P. C. S. Scholtens, "Assessment of the merits of CMOS technology scaling for analog circuit design," in Proc. ESSCIRC, 2004, pp. 57-63.
17. T. Yao, M. Gordon, K. Yau, M. T. Yang, and S. P. Voinigescu, "60-GHz PA and LNA in 90-nm RF-CMOS," presented at the IEEE RFIC Symp., San Francisco, CA, Jun. 2006, RMO2C-2.
18. T. O. Dickson and S. P. Voinigescu, "SiGe BiCMOS topologies for low-voltage millimeter-wave frequency dividers and voltage-controlled oscillators," in Si Monolithic Integrated Circuits in RF Systems, Tech. Dig., Jan. 2006, pp. 273-276.
19. G. Vendelin, A. M. Pavio, and U. L. Rohde, Microwave Circuit Design Using Linear and Nonlinear Techniques, 2nd ed. New York: Wiley, 2005.
20. S. P. Voinigescu, M. C. Maliepaard, J. L. Showell, G. E. Babcock, D. Marchesan, M. Schroter, P. Schvan, and D. L. Harame, "A scalable high-frequency noise model for bipolar transistors with application to optimal transistor sizing sizing for low-noise amplifier design," IEEE J. Solid-State Circuits, vol. 32, no. 9, pp. 1430-1439, Sep. 1997.
21. H. Tran, F. Pera, D. S. McPherson, D. Viorel, and S. P. Voinigescu, "6-kOhm, 43-Gb/s differential transimpedance-limiting amplifier with auto-zero feedback and high dynamic range," IEEE J. Solid-State Circuits, vol. 39, no. 10, pp. 1680-1689, Oct. 2004.
22. A. N. Karanicolas, "A 2.7-V 900-MHz CMOS LNA and mixer," IEEE J. Solid-State Circuits, vol. 31, no. 12, pp. 1939-1944, Dec. 1996.
23. C. Kromer, G. Sialm, C. Berger, T. Morf, M. Schmatz, F. Ellinger, D. Erni, G.-L. Bona, and H. Jackel, "A 100 mW 4 × 10 Gb/s transceiver in 80 nm CMOS for high-density optical interconnects," in IEEE ISSCC Dig. Tech. Papers, Feb. 2005, pp. 334-335.
24. T. O. Dickson, R. Beerkens, and S. P. Voinigescu, "A 2.5-V 45-Gb/s decision circuit using SiGe BiCMOS logic," IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 994-1003, Apr. 2005.
25. H.-M. Rein and M. Moller, "Design considerations for very-high-speed Si bipolar IC's operating up to 50 Gb/s," IEEE J. Solid-State Circuits, vol. 31, no. 8, pp. 1076-1090, Aug. 1996.
26. T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits. New York: Cambridge Univ. Press, 1998.
27. T. O. Dickson, M.-A. LaCroix, S. Boret, D. Gloria, R. Beerkens, and S. P. Voinigescu, "30-100 GHz inductors and transformers for millimeter-wave (Bi)CMOS integrated circuits," IEEE Trans. Microw. Theory Tech., vol. 53, no. 1, pp. 123-133, Jan. 2005.
28. J. Kim, J.-K. Kim, B.-J. Lee, M.-S. Hwang, H.-R. Lee, S.-H. Lee, N. Kim, D.-K. Jeong, and W. Kim, "Circuit techniques for a 40-Gb/s transmitter in 0.13- μm CMOS," in IEEE ISSCC Dig. Tech. Papers, Feb. 2005, pp. 150-151.
29. MAX 0.13-μm SiGe:C BiCMOS technology," in Proc. BCTM, 2003, pp. 199-202.
30. P. Westergaard, T. O. Dickson, and S. P. Voinigescu, "A 1.5-V, 20/30-Gb/s CMOS backplane driver with digital pre-emphasis," in Proc. IEEE CICC, Orlando, FL, Oct. 2004, pp. 23-26.
31. C. Enz, "An MOS transistor model for RFIC design valid in all regions of operation," IEEE Trans. Microw. Theory Tech., vol. 50, no. 1, pp. 342-359, Jan. 2002.
32. L. Larson, "Silicon technology tradeoffs for radio-frequency/mixed- signal systems-on-a-chip," IEEE Trans. Electron Devices, vol. 50, no. 3, pp. 683-699, Mar. 2003.
33. S. P. Voinigescu, M. Tazlauanu, P. C. Ho, and M. T. Yang, "Direct extraction methodology for geometry-scalable RF-CMOS models," in Proc.IEEE ICMTS, Mar. 2004, pp. 235-240.
34. T of millimeter-wave MODFETs," IEEE Electron Device Lett., vol. 10, no. 7, pp. 291-293, Jul. 1989.
35. H. M. J. Boots, G. Doornbos, and A. Heringa, "Scaling of characteristic frequencies in RF CMOS," IEEE Trans. Electron Devices, vol. 51, no. 12, pp. 2102-2108, Dec. 2004.