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Volumn , Issue , 2004, Pages 233-236
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A low power 13-Gb/s 2̂7-1 Pseudo random bit sequence generator IC in 120nm bulk CMOS
a a |
Author keywords
CML; Flip Flop; Pseudo Random
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Indexed keywords
CMOS INTEGRATED CIRCUITS;
COMPUTER HARDWARE;
DATA COMMUNICATION EQUIPMENT;
EMITTER COUPLED LOGIC CIRCUITS;
FLIP FLOP CIRCUITS;
LOGIC DESIGN;
NATURAL FREQUENCIES;
THRESHOLD VOLTAGE;
CIRCUIT DESIGNS;
FLIP-FLOP;
POWER CONSUMPTION;
PSEUDO RANDOM;
RANDOM NUMBER GENERATION;
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EID: 14244258872
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1145/1016568.1016630 Document Type: Conference Paper |
Times cited : (18)
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References (7)
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