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Volumn , Issue , 2004, Pages 233-236

A low power 13-Gb/s 2̂7-1 Pseudo random bit sequence generator IC in 120nm bulk CMOS

Author keywords

CML; Flip Flop; Pseudo Random

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER HARDWARE; DATA COMMUNICATION EQUIPMENT; EMITTER COUPLED LOGIC CIRCUITS; FLIP FLOP CIRCUITS; LOGIC DESIGN; NATURAL FREQUENCIES; THRESHOLD VOLTAGE;

EID: 14244258872     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1016568.1016630     Document Type: Conference Paper
Times cited : (18)

References (7)
  • 6
    • 0034790426 scopus 로고    scopus 로고
    • A 0.13μm CMOS platform with Cu/Low-k interconnects for system on chip applications
    • IEEE
    • T. Schiml et al. A 0.13μm CMOS Platform with Cu/Low-k Interconnects for System On Chip Applications. In VLSI Digest of Technical Papers, pages 101-102. IEEE, 2001.
    • (2001) VLSI Digest of Technical Papers , pp. 101-102
    • Schiml, T.1
  • 7
    • 0346935288 scopus 로고    scopus 로고
    • High speed CMOS circuits up to 40 Gb/s and 50 GHz
    • San Diego. USA. Nov. IEEE, invited paper
    • H. Wohlmuth, D. Kehrer, M. Tiebout, H. Knapp, M. Wurzer, and W. Simbürger. High Speed CMOS Circuits up to 40 Gb/s and 50 GHz. In GaAs IC, San Diego. USA. Nov. 2003. IEEE, invited paper.
    • (2003) GaAs IC
    • Wohlmuth, H.1    Kehrer, D.2    Tiebout, M.3    Knapp, H.4    Wurzer, M.5    Simbürger, W.6


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.