Algorithmic design methodologies and design porting of wireline transceiver IC building blocks between technology nodes

Proceedings of the Custom Integrated Circuits Conference

Volumn 2005, Issue , 2005, Pages 111-118

  Voinigescu, S P ^a   Dickson, T O ^a   Chalvatzis, T ^a   Hazneci, A ^a   Laskin, E ^a   Beerkens, R ^b   Khalid, I ^b  

^a UNIVERSITY OF TORONTO   (Canada)

^b STMICROELECTRONICS   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

OSCILLATORS (ELECTRONIC); SPURIOUS SIGNAL NOISE; SYSTEMS ANALYSIS; TOPOLOGY;

LOW NOISE OSCILLATORS; WAVE SHAPE CONTROL;

CMOS INTEGRATED CIRCUITS;

EID: 33749523503     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2005.1568621     Document Type: Conference Paper

References (23)

1. T. Dickson et al., "A 72Gb/s 231-1 PRBS Generator in SiGe BiCMOS Technology," ISSCC Digest, pp.342-343, Feb. 2005.
2. S.P. Voinigescu, et al., "A comparison of Si CMOS, SiGe BiCMOS, and InP HBT technologies for high-speed and millimeter-wave ICs," SiRF-2004, pp. 111-114, Sept. 2004.
3. S.P. Voinigescu, "RF and High-Speed Integrated Circuits," ECE1364S, lecture notes and midterm exam, University of Toronto, 2005.
4. "International Technology Roadmap for Semiconductors 2003 Edition interconnect," ITRS, 2003/2004.
5. G.D. Vendelin, et al., Microwave Circuit Design Using Linear and Nonlinear Techniques, Toronto, John Wiley & Sons, 1990.
6. S.P. Voinigescu et al, "A scalable high-frequency noise model for bipolar transistors with application to optimal transistor sizing for low-noise amplifier design," IEEE J. Solid-State Circuits, vol. 32, no. 9, Sept. 1997.
7. A.N. Karanicolas, "A 2.7-V 900-MHz CMOS LNA and Mixer," IEEE J. Solid-State Circuits, vol. 31, no. 12, pp.1939-1944, Dec. 1996.
8. C. Kromer, et al. "A 100mW 4×10Gb/s Transceiver in 80nm CMOS for High-density Optical interconnects," ISSCC Digest, pp.334-335, 2005.
9. H. Tran et al, "6-kΩ, 43-Gb/s differential transimpedance-limiting amplifier with auto-zero feedback and high dynamic range," IEEE GaAs IC Symp. Tech. Dig., pp. 241-244, Nov. 2003.
10. M.. Meghelli, "A 108Gb/s 4:1 Multiplexer in 0.13 μm SiGe-Bipolar Technology," ISSCC Digest, pp.236-237, Feb. 2004.
11. MAX 0.13 μm SiGe:C BiCMOS technology,"Proc. IEEE BCTM, Sept. 2003.
12. G. Freeman et al. "Transistor Design and Application Considerations for >200 GHz SiGe HBTs," IEEE Trans ED, Vol.50, No.3, pp.645-655, 2003.
13. T.O. Dickson et al., "A 2.5-V, 40-Gb/s Decision Circuit Using SiGe BiCMOS Logic," Dig. Symp. VLSI Circuits, pp. 206-209, June 2004.
14. M. Rodwell, et al., "Transistor and Circuit Design for 100-200 GHz ICs," IEEE CSICS Technical Digest, pp.207-210, Oct. 2004.
15. J. Kim, et al., "Circuit Techniques for a 40Gb/s Transmitter in 0.13nm CMOS," ISSCC Digest, pp.150-151, Feb. 2005.
16. K. Kanda, et al., "40Gb/s 4:1 MUX/1:4 DEMUX in 90nm Standard CMOS," ISSCC Digest, pp.152-153, Feb. 2005.
17. D. Kehrer et al., "A 60Gb/s 2:1 Selector in 90nm CMOS," IEEE CSICS Digest, pp.105-108, Oct. 2004.
18. F. Ellinger, et al., "60 GHz VCO with Wideband Tuning Range Fabricated on VLSI SOI CMOS Technology," IEEE MTT-S Digest, pp.1329-1332, June 2004.
19. J. Kim, et al., "A 44GHz Differentially Tuned VCO with 4GHz Tuning Range in 0.12nm SOI CMOS Technology," ISSCC Digest, pp.416-417, Feb. 2005.
20. P.-C. Huang, et al., "A 114GHz VCO in 0.13nm CMOS Technology," ISSCC Digest, pp.404-405, Feb. 2005.
21. C. Lee, et al., "SiGe BiCMOS 65-GHz BPSK Transmitter and 30 to 122 GHz LC-Varactor VCOs with up to 21% Tuning Range," IEEE CSICS, Technical Digest, pp.179-182, Oct. 2004.
22. S. Kumar, et al., "A network on chip architecture and design methodology," in IEEE Computer Society Annual Symposium on VLSI, pp. 105-112, April 2002.
23. A. Hazneci and S. P. Voinigescu, "49-Gb/s, 7-Tap Transversal Filter in 0.18μm SiGe BiCMOS for Backplane Equalization," IEEE CSICS, Technical Digest, pp.101-104, Oct.2004.