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Volumn 35, Issue 9, 2000, Pages 1266-1270

3.3-V 21-Gb/s PRBS generator in AlGaAs/GaAs HBT technology

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL INTEGRATED CIRCUITS; ELECTRIC GENERATORS; ELECTRIC NETWORK TOPOLOGY; ELECTRIC POTENTIAL; SEMICONDUCTING ALUMINUM COMPOUNDS; SEMICONDUCTING GALLIUM ARSENIDE;

EID: 0034270358     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.868034     Document Type: Article
Times cited : (24)

References (18)
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  • 5
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  • 6
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    • Sept.
    • T. Otsuji, K. Murata, T. Enoki, and Y. Umeda, "An 80 Gbit/s multiplexer IC using InAlAs/InGaAs/InP HEMTs," IEEE J. Solid State Circuits, vol. 33, pp. 1321-1327, Sept. 1998.
    • (1998) IEEE J. Solid State Circuits , vol.33 , pp. 1321-1327
    • Otsuji, T.1    Murata, K.2    Enoki, T.3    Umeda, Y.4
  • 7
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    • Silicon bipolar IC for PRBS testing generates adjustable bit rates up to 25 Gbit/S
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    • (1997) Electron. Lett. , vol.33 , pp. 2022-2023
    • Schumann, F.1    Bock, J.2
  • 10
    • 0027813979 scopus 로고
    • A 12.5 Gb/s si bipolar IC for PRBS generation and bit error detection up to 25 Gb/s
    • Dec.
    • M. Bußmann, U. Langmann, W. J. Hillery, and W. W. Brown, "A 12.5 Gb/s Si bipolar IC for PRBS generation and bit error detection up to 25 Gb/s," IEEE J. Solid State Circuits, vol. 28, pp. 1303-1309, Dec. 1993.
    • (1993) IEEE J. Solid State Circuits , vol.28 , pp. 1303-1309
    • Bußmann, M.1    Langmann, U.2    Hillery, W.J.3    Brown, W.W.4
  • 11
    • 0028516012 scopus 로고
    • A voltage compensated series-gate bipolar circuit operating at sub-2V
    • Oct.
    • H. Sato, K. Ueda, N. Sasaki, T. Ikeda, and K. Mashiko, "A voltage compensated series-gate bipolar circuit operating at sub-2V," IEEE J. Solid State Circuits, vol. 29, pp. 1200-1204, Oct. 1994.
    • (1994) IEEE J. Solid State Circuits , vol.29 , pp. 1200-1204
    • Sato, H.1    Ueda, K.2    Sasaki, N.3    Ikeda, T.4    Mashiko, K.5
  • 12
    • 0029255547 scopus 로고
    • 1.65 Gb/s 60 m W 4: 1 multiplexer and 1.8 Gb/s 80 m W 1:4 demultiplexer ICs using 2v 3-level series-gating ECL circuits
    • T. Kuroda, T. Fujita, Y. Itabashi, S. Kabumoto, M. Noda, and A. Kanuma, "1.65 Gb/s 60 m W 4: 1 multiplexer and 1.8 Gb/s 80 m W 1:4 demultiplexer ICs using 2v 3-level series-gating ECL circuits," in 1995 IEEE Int. Solid-State Circuits Conf., 1995, pp. 36-37.
    • (1995) 1995 IEEE Int. Solid-state Circuits Conf. , pp. 36-37
    • Kuroda, T.1    Fujita, T.2    Itabashi, Y.3    Kabumoto, S.4    Noda, M.5    Kanuma, A.6
  • 13
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    • Kishine, K.1    Kobayashi, Y.2    Ichino, H.3
  • 16
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  • 17
    • 0030405059 scopus 로고    scopus 로고
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    • T. Otsuji, M. Yoneyama, K. Murata, and E. Sano, "A super-dynamic flip-flop circuit for broadband applications up to 24 Gbit/s utilizing production-level 0.2-um GaAs MESFETS," in IEEE GaAs IC Symp. Tech. Dig., 1996, pp. 145-148.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.