1.5-V low supply voltage 43-Gb/s delayed flip-flop circuit

Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit)

Volumn , Issue , 2003, Pages 169-172

  Amamiya, Yasushi ^a   Suzuki, Yasuyuki ^a   Yamazaki, Jin ^a   Fujihara, Akira ^a   Tanaka, Shinichi ^a   Hida, Hikaru ^a  

^a NEC CORPORATION   (Japan)

Author keywords

D F F; High speed; InP HBT; Low supply voltage

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMBINATORIAL CIRCUITS; DELAY CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; HETEROJUNCTION BIPOLAR TRANSISTORS; PHASE CHANGING CIRCUITS; SWITCHING CIRCUITS; TIMING CIRCUITS;

CLOCK PHASE MARGIN; DELAYED FLIP FLOP CIRCUIT; LOW SUPPLY VOLTAGE; PARALLEL CURRENT SWITCHING; POWER DISSIPATION;

FLIP FLOP CIRCUITS;

EID: 0346935199     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/gaas.2003.1252387     Document Type: Conference Paper

References (7)

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7. Amamiya, Y., et al., "40-Gb/s Optical Receiver IC Chipset-including a Transimpedance Amplifier, a Differential Amplifier, and a Decision Circuit - using GaAs-based HBT Technology," 2002 IEEE MTT-S Dig., pp. 87-90, 2002.