Analog/RF circuit design techniques for nanometerscale IC technologies

Proceedings of ESSCIRC 2005: 31st European Solid-State Circuits Conference

Volumn , Issue , 2005, Pages 45-53

  Nauta, Bram ^a   Annema, Anne Johan ^a  

^a UNIVERSITY OF TWENTE   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CURRENTS; GATES (TRANSISTOR); LEAKAGE CURRENTS; LOGIC DESIGN; POWER SUPPLY CIRCUITS; THIN FILM TRANSISTORS;

ANALOG DESIGN; CMOS TECHNOLOGY; NANOMETERS; SUPPLY VOLTAGE;

CMOS INTEGRATED CIRCUITS;

EID: 33749178207     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIR.2005.1541556     Document Type: Conference Paper

References (54)

1. Y. Taur, "CMOS design near the limit of scaling," IBM J. Res. & Dev. Vol. 46, No. 2/3, pp. 213-222, 2002
2. D.D. Buss, "Technology in the Internet Age", in Dig. Tech. Papers, ISSCC 2002, pp. 18-21
3. A.J. Annema, B. Nauta, R. van Langevelde and H. Tuinhout, "Designing outside rails constraints", in Dig. Tech. Papers, ISSCC 2004, pp. 134-135
4. P. van Zeijl, J.W.Th. Eikenbroek, P.P. Vervoort, S. Setty, J. Tangenberg, G. Shipton, E. Kooistra, I.C. Keekstra, D. Belot, K. Visser, E. Bosma, S.C. Blaakmeer, "A Bluetooth radio in 0.18-μm CMOS", IEEE J. Solid-State Circuits, vol. 37, pp. 1679-1687, December 2002.
5. H. Darabi, S. Khorram, Z. Zhou, T. Li, B. Marholev, J. Chiu,J. Castaneda, E. Chien, S. Anand, S. Wu, M. Pan, R. Roufoogaran,H. Kim, P. Lettieri, B. Ibrahim, J. Rael, L. Tran, E. Geronaga, H. Yeh, T. Frost, J. Trachewsky, A. Rofougaran, "A Fully Integrated SoC for 802.11b in 0.18um CMOS", in Dig. Tech. Papers, ISSCC 2005, pp 96-97
6. S. Mehta, D. Weber, M. Terrovitis, K. Onodera, M. Mack, B. Kaczynski, H. Samavati, S. Jen, W. Si, M.L. Lee, K. Singh, S. Mendis, P. Husted, N. Zhang, B. McFarland, D. Su, T. Meng, B. Wooley, "802.11g WLAN SoC",in Dig. Tech. Papers, ISSCC 2005, pp 94-95
7. Adiseno, M. Ismail, H. Olsson, "A wide-band RF front-end for multiband multistandard high-linearity low-IF wireless receivers", IEEE J. of Solid-State Circuits, vol. 37, pp. 1162-1168, September 2002.
8. V.J. Arkesteijn, E.A.M. Klumperink, B. Nauta, "A wideband high-linearity RF receiver front-end in CMOS", in Proc. ESSCIRC, pp. 71-74, 2004.
9. M.J.M. Pelgrom, H.P. Tuinhout, and M. Vertregt, "Transistor matching in analog CMOS applications", in IEDM Technical Digest, pp. 915-918, 1998
10. M.J.M. Pelgrom, A.C.J. Duinmaijer, and A.P.G. Welbers, "Matching properties of MOS transistors," IEEE J. Solid-State Circuits, Vol. 24, No. 10, pp. 1433-1440, 1989
11. K. Bult, "Analog Design in Deep Sub-Micron CMOS", in Proc. ESSCIRC, pp. 11-17, 2000
12. J. Dubois, J. Knol, M. Bolt, H. Tuinhout, J. Schmitz, and P. Stolk, "Impact of source/drain implants on threshold voltage matching in deep sub-micron CMOS technologies", in Proc. ESSDERC, pp. 115-118, 2002
13. A.J. Scholten, L.F. Tiemeijer, R. van Langevelde, R.J. Havens, A.T.A. Zegers-van Duijnhoven and V.C. Venezia, "Noise Modeling for RF CMOS Circuit Simulation," IEEE tr. Electron Devices, Vol. ED-50, No. 3, pp. 618-632, 2003.
14. R. van Langevelde, J.C.J. Paasschens, A.J. Scholten, R.J. Havens, L.F. Tiemeijer and D.B.M. Klaassen, "New Compact Model for Induced Gate Current Noise," in IEDM Technical Digest, pp. 867-870, 2003
15. A. Stek, G.W. de Jong, T.P.H.G. Jansen, J.R.M. Bergervoet and P.H. Woerlee, "Circuit Design and Noise Considerations for Future Blu-ray Disc Optical Storage Technology", in Dig. Tech. Papers, ISSCC 2004, pp. 136-137
16. F. Boeuf, F. Arnaud, M.T. Basso, D. Sotta, F. Wacquant, J. Rosa, N. Bicais-Lepinay, H. Bernard, J. Bustos, S. Manakli, M. Gaillardin, J. Grant, T. Skotnicki, B. Tavel, B. Duriez, M. Bidaud, P. Gouraud, C. Chaton, P. Morin, J. Todeschini, M. Jurdit, L. Pain, V. De-Jonghe, R. El-Farhane, and S. Jullian, "A Conventional 45nm CMOS node Low-Cost Platform for General Purpose and Low Power Application", in Proc. IEDM 2004, December 2004, pp. 425-428
17. T. Skotnicki, J.A. Hutchby, T.J. King, H.S.P. Wong and F. Boeuf, "The end of CMOS scaling",IEEE Circuits & Devices magazine, Januari 2005, pp. 16-26
18. L. Chang, Y.K. Choi, J. Kedzierski, N. Lindert, P. Xuan, J. Bokor, C. Hu and T.J. King, "Moore's law Lives on", IEEE Circuits & Circuits magazine, Januari 2003, pp. 35-42
19. D. Hisamoto, T. Kaga, Y. Kawamoto and E. Takeda, "A Fully Depleted Lean-channel Transistor (DELTA) - A novel vertical ultra thin SOI MOSFET", in Proc. IEDM 1989, pp. 833-836
20. D. Hisamoto, W.C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, T.J. King, J. Bokor and C. Hu, "FinFET - A self-aligned double-gate MOSFET scalable beyond 20nm", IEEE tr. Electron Devices, December 2000, pp. 2320-2325
21. E.J. Nowak, I. Aller, T. Ludwig, K. Kim, R.V. Joshi, C.T. Chuang, K. Bernstein and R. Puri, "Turning Silicon on its Edge", IEEE Circuits & Devices Magazine, januari 2004, pp. 20-31
22. X. Huang, W.C. Lee; C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.K. Choi,K. Asano, V. Subramanian, T.J. King, J. Bokor and C. Hu, "Sub-50 nm P-Channel FinFET", IEEE tr. Electron Devices, vol. 48, May 2001, pp. 880-886
23. E.J. Nowak, "Maintaining the benefits of CMOS scaling when scaling bogs down", IBM J. Res. & Dev.,vol. 46, March 2002, pp.169-179
24. th Int'l Symposium on Quality Electronic Design, 2004, pp. 511-516
25. S. Xiong and J. Bokor, "Sensitivity of Double-Gate and FinFET Devices to Process Variations", IEEE tr. Electron Devices, November 2003, pp. 2255-2261
26. L. Chang, K.J. Yang, Y.C. Yeo, I. Polishchuk, T.J. King and C. Hu, "Direct-Tunneling Gate Leakage Current in Double-Gate and Ultrathin Body MOSFETs", IEEE tr. Electron Devices, vol. 12, December 2002, pp. 2288-2294
27. L.Chang, M. Ieong and M. Yang, "CMOS Circuit Performance Enhancement by Surface Orientation Optimization", IEEE tr. Electron Devices,vol. 51, October 2004, pp. 1621-1627
28. E. Pop, R. Dutton, and K. Goodson, "Thermal Analysis of Ultra-Thin Body Device Scaling", in Proc IEDM 2003, pp. 883-886
29. B.M. Tenbroek, W. Redman-White, M.S.L. Lee, R.J.T. Bunyan, M.J. Uren, and K.M. Brunson, "Characterization of layout dependent thermal coupling in SOI CMOS current mirrors", IEEE tr. Electron Devices, Volume 43, Issue 12, Dec. 1996, pp. 2227-2232
30. M. Horowitz, W. Dally, "How scaling will change processor architecture", in Dig. Tech. Papers ISSCC 2004, pp. 132-133
31. A. Agarwal, B. C. Paul, and K. Roy, "Process variation in nano-scale memories: Failure analysis and process tolerant architecture", in Proc. CICC 2004, pp. 353-356
32. H. Veendrick, "Digital goes Analog", in Proc. ESSCIRC 1998, pp 44-50
33. J. Kim, M.A. Horowitz, "An efficient digital sliding controller for adaptive power-supply regulation", IEEE J. Solid-State Circuits, vol. 37, pp. 639-647, May 2002
34. M. Nakai, S. Akui, K. Seno, R. Meguro, T. Seki, T. Kondo, A. Hashiguchi, K. Kumano and M. Shimura, "Dynamic Voltage and Frequency Management for a Low-Power Embedded Microprocessor", IEEE J. Solid-State Circuits, vol. 40, january 2005, pp. 28-35
35. A. Muhtaroglu, G.Taylor and T. Rahal-Arabi, "On-Die Froop Detector for Analog Sensing of Power Supply Noise", IEEE J. Solid-State Circuits, vol. 4, April 2004, pp. 651-660
36. D. Schinkel, R. P. de Boer, A. J. Annema, A. J. M. van Tuijl, "A 1-V 15μW high-precision temperature switch", in Proc. ESSCIRC 2001, pp. 104-107
37. T.Tsukada, Y. Hashimoto, K. Sakata, H. Okada and K. Ishibashi, "An On-Chip Active Decoupling Circuit to Suppress Crosstalk in Deep-Submicron CMOS Mixed-Signal SoCs", IEEE J. Solid-State Circuits, vol. 40, Januari 2005, pp. 67-79
38. G.W. den Besten, B. Nauta, "Embedded 5 V-to-3.3 V voltage regulator for supplying digital IC's in 3.3 V CMOS technology", IEEE J. Solid-State Circuits, vol. 33, pp. 956-962, July 1998.
39. P. Hazucha, T. Kamik, B. Bloechel, C. Parsons, D. Finan, S. Borkar, "An area-efficient, integrated, linear regulator with ultra-fast load regulation", Symp. VLSI Circuits Dig. 18, pp. 218-221, June 2004.
40. A.J. Annema, G.J.G.M. Geelen, P.C. de Jong, "5.5-V I/O in a 2.5-V 0.25-μm CMOS technology", IEEE J. Solid-State Circuits, vol. 36, pp. 528-538, March 2001.
41. R. Ho. K.W. Mai, and M. Horowitz, "The Future of Wires," Proc. IEEE, pp. 490-504, Apr., 2001.
42. R. Ho, K. Mai, and M. Horowitz, "Efficient On-Chip Global Interconnects," 2003 VLSI Circuits Symposium, pp. 271-274, June, 2003.
43. R.T. Chang, N. Talwalkar, C.P. Yue, and S.S. Wong, "Near Speed-of-Light Signaling Over On-Chip Electrical Interconnects," IEEE J. Solid-State Circuits, vol. 38, pp. 834-838, May, 2003.
44. D. Schinkel, E. Mensink, E.A.M. Klumperink, A.J.M. van Tuijl, "A 3Gb/s/ch Trnasceiver for RC-limited On-Chip Interconnects. ISSCC 2005 pp 386-387
45. B. Murmann, B.E. Boser, "A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification", IEEE J. of Solid-State Circuits, vol. 38, pp. 2040-2050, December 2003.
46. X. Wang, P.J. Hurst, S.H. Lewis, "A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration", IEEE J. Solid-State Circuits, vol. 39, pp. 1799-1808, November 2004.
47. G. Brenna, D. Tschopp, J. Rogin, I. Kouchev, Q. Huang, "A 2-GHz carrier leakage calibrated direct-conversion WCDMA transmitter in 0.13-μm CMOS", IEEE J. of Solid-State Circuits, vol. 39, pp. 1253-1262, August 2004.
48. J. Crols, M. Steyaert, "Switched-opamp: An approach to realize full CMOS switched-capacitor circuits at very low power supply voltages", IEEE J. of Solid-State Circuits, vol. 29, pp. 936-942, August 1994.
49. E.A.M. Klumperink, S.M. Louwsma, G.J.M. Wienk, B. Nauta, "A CMOS switched transconductor mixer", IEEE J. of Solid-State Circuits, vol. 39, pp. 1231-1240, August 2004.
50. F. Bruccoleri, E.A.M. Klumperink, B. Nauta, "Wide-band CMOS low-noise amplifier exploiting thermal noise canceling", IEEE J. of Solid-State Circuits, vol. 39, pp. 275-282, February 2004.
51. A.P. van der Wel, E.A.M. Klumperink, L.K.J. Vandamme, B. Nauta; "Modeling random telegraph noise under switched bias conditions using cyclostationary RTS noise", IEEE Trans. Electron Devices, Vol. 50, pp. 1378-1384, May 2003.
52. T. Sowlati, D.M.W. Leenarts, "A 2.4-GHz 0.18-um CMOS self-biased cascode power amplifier", IEEE J. Solid-State Circuits, Vol. 38, Aug. 2003, pp. 1318-1324
53. B. Serneels, T. Piessens, M. Steyaert, W. Dehaene," A high voltage output driver in a 2.5V 0.25um CMOS technology.
54. A.P. van der Wel, S.L.J. Gierkink, R.C. Frye, V.Boccuzzi, B. Nauta; A robust 43-GHz VCO in CMOS for OC-768 SONET applications, IEEE J. Solid-State Circuits, vol. 39, pp. 1159-1163, July 2004.