Impact of source/drain implants on threshold voltage matching in deep sub-micron CMOS technologies

European Solid-State Device Research Conference

Volumn , Issue , 2002, Pages 115-118

  Dubois, Jerôme ^a   Knol, Johan ^a   Bolt, Mike ^a   Tuinhout, Hans ^b   Schmitz, Jurriaan ^b   Stolk, Peter ^b  

^a NXP SEMICONDUCTORS   (Netherlands)

^b NONE   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

THRESHOLD VOLTAGE;

DEEP SUB-MICRON; IMPLANT ENERGY; MATCHING PERFORMANCE; NEW MECHANISMS; OXIDE LAYER THICKNESS; POLYSILICON GATES; SOURCE-DRAIN IMPLANTS; VOLTAGE MATCHING;

CMOS INTEGRATED CIRCUITS;

EID: 84907684167     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2002.194883     Document Type: Conference Paper

References (5)

1. P.A. Stolk et al. 'CMOS Device Optimization for Mixed-Signal Technologies' Technical Digest IEDM-01, pp. 215-218 (2001)
2. Marcel J.M. Pelgrom, Hans P. Tuinhout and Maarten Vertregt 'Transistor matching in analog CMOS applications', Technical Digest IEDM-98, pp. 915-918 (1998)
3. P.A. Stolk, F.P. Widdershoven and D.B.M. Klaassen, 'Modeling statistical dopant fluctuations in MOS transistors', IEEE Transactions on Electron Devices, vol.45, no.9, p.1960-71, (1998).
4. J.A. Croon, H.P. Tuinhout, R. Difrenza, J. Knol, A.J. Moonen,S. Decoutere, H.E. Maes, W. Sansen, 'A comparison of extraction techniques for threshold voltage mismatch', to be published at ICMTS 2002.
5. J. Schmitz, H.P. Tuinhout, A.H. Montree, Y.V. Ponomarev, P.A. Stolk and P.H. Woerlee, 'Gate polysilicon optimization for deep-submicron MOSFETs', Proc. ESSDERC 1999, 156-159 (1999).