Designing outside rail constraints

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 47, Issue , 2004, Pages

  Annema, Anne Johan ^a   Nauta, Bram ^a   Van Langevelde, Ronald ^b   Tuinhout, Hans ^b  

^a UNIVERSITY OF TWENTE   (Netherlands)

^b PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

HARMONIC CURRENTS; RAIL CONSTRAINTS;

ELECTRIC CURRENTS; ELECTRIC DISTORTION; ELECTRIC POTENTIAL; ELECTRIC POWER UTILIZATION; GATES (TRANSISTOR); MATHEMATICAL MODELS; PERFORMANCE; SIGNAL TO NOISE RATIO;

CMOS INTEGRATED CIRCUITS;

EID: 2442640106     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. A.J. Annema, "Analog Circuit Performance and Process Scaling," IEEE Transactions of Circuits and Systems II, vol. 46, pp. 711-725, 1999.
2. R. van Langevelde et al., "Gate Current: Modelling, DL Extraction and Impact on RF Performance," IEDM 2001 Technical Digest, pp. 289-292
3. A. Scholten et al, "Compact Modeling of Drain and Gate Current Noise for RF CMOS," IEDM 2002, Technical Digest
4. J. Dubois et al, "Impact of Source/Drain Implants on Threshold Voltage Matching in Deep Sub-micron CMOS Technologies" ESSDERC 2002
5. A.J. Annema et al, "5.5V Tolerant I/O in a 2.5V 0.25um CMOS Technology," IEEE J. Solid-State Circuits, pp. 528-538, 2001.