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Volumn 2006, Issue , 2006, Pages 223-230

Electrothermal engineering in the nanometer era: From devices and interconnects to circuits and systems

Author keywords

[No Author keywords available]

Indexed keywords

CHIP COOLING; CHIP LEAKAGE ESTIMATION; INTEGRATED NETWORKS; POWER DISSIPATION;

EID: 33748607434     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (24)

References (48)
  • 1
    • 0033362679 scopus 로고    scopus 로고
    • Technology and design challenges for low power and high performance microprocessors
    • V. De and S. Borkar, "Technology and design challenges for low power and high performance microprocessors," ISLPED, 1999, pp. 163-168.
    • (1999) ISLPED , pp. 163-168
    • De, V.1    Borkar, S.2
  • 4
    • 0034429730 scopus 로고    scopus 로고
    • CMOS circuit technology for sub-ambient temperature operation
    • I. Aller et al., "CMOS circuit technology for sub-ambient temperature operation," ISSCC, 2000, pp. 214-215.
    • (2000) ISSCC , pp. 214-215
    • Aller, I.1
  • 5
    • 0041633858 scopus 로고    scopus 로고
    • Parameter variations and impact on circuits and microarchitecture
    • S. Borkar et al., "Parameter variations and impact on circuits and microarchitecture," DAC, 2003, pp. 338-342.
    • (2003) DAC , pp. 338-342
    • Borkar, S.1
  • 6
    • 2442526254 scopus 로고    scopus 로고
    • Beat the heat
    • P. E. Ross, "Beat the heat," Spectrum, IEEE, Vol. 41, pp. 38-43, 2004.
    • (2004) Spectrum, IEEE , vol.41 , pp. 38-43
    • Ross, P.E.1
  • 7
    • 0027187249 scopus 로고
    • Timing-, heat- and area-driven placement using self-organizing semantic maps
    • C. X. Zhang, "Timing-, heat- and area-driven placement using self-organizing semantic maps," ISCAS, 1993, pp. 2067-2070.
    • (1993) ISCAS , pp. 2067-2070
    • Zhang, C.X.1
  • 8
    • 0032139246 scopus 로고    scopus 로고
    • ILLIADS-T: An electrothermal timing simulator for temperature-sensitive reliability diagnosis of CMOS VLSI chips
    • Y-K Cheng et al., "ILLIADS-T: An electrothermal timing simulator for temperature-sensitive reliability diagnosis of CMOS VLSI chips," IEEE TCAD, Vol. 17, pp.668-681, 1998.
    • (1998) IEEE TCAD , vol.17 , pp. 668-681
    • Cheng, Y.-K.1
  • 9
    • 0031198450 scopus 로고    scopus 로고
    • ITEM: A Temperature-dependent electromigration reliability diagnosis tool
    • C. C. Teng et al., "iTEM: A Temperature-dependent electromigration reliability diagnosis tool," IEEE TCAD, Vol. 16, pp. 882-893, 1997.
    • (1997) IEEE TCAD , vol.16 , pp. 882-893
    • Teng, C.C.1
  • 10
    • 20444496778 scopus 로고    scopus 로고
    • Modeling and analysis of non-uniform substrate temperature effects on global ULSI interconnects
    • A. H. Ajami, K. Banerjee and M. Pedram, "Modeling and analysis of non-uniform substrate temperature effects on global ULSI interconnects", IEEE TCAD, Vol. 24, pp. 849-861, 2005.
    • (2005) IEEE TCAD , vol.24 , pp. 849-861
    • Ajami, A.H.1    Banerjee, K.2    Pedram, M.3
  • 11
    • 0041384477 scopus 로고    scopus 로고
    • Thermal placement algorithm based on heat conduction analogy
    • J. Lee, "Thermal placement algorithm based on heat conduction analogy," IEEE Trans. on Components and Packaging Tech., Vol. 26, pp.473-482, 2003.
    • (2003) IEEE Trans. on Components and Packaging Tech. , vol.26 , pp. 473-482
    • Lee, J.1
  • 12
    • 0033871060 scopus 로고    scopus 로고
    • Cell-level placement for improving substrate thermal distribution
    • C. H. Tsai and S. M. Kang, "Cell-level placement for improving substrate thermal distribution," IEEE TCAD, Vol. 19, pp. 253-266, 2000.
    • (2000) IEEE TCAD , vol.19 , pp. 253-266
    • Tsai, C.H.1    Kang, S.M.2
  • 13
    • 84944378006 scopus 로고
    • Measurement and modeling of self-heating in SOI nMOSFETs
    • L.T. Su, et al., "Measurement and modeling of self-heating in SOI nMOSFETs", IEEE TED, Vol. 41, pp. 69-75, 1994.
    • (1994) IEEE TED , vol.41 , pp. 69-75
    • Su, L.T.1
  • 14
    • 0031236694 scopus 로고    scopus 로고
    • Heating mechanisms of LDMOS and LIGBT in ultra-thin SOI
    • Y-K. Leung, et al., "Heating mechanisms of LDMOS and LIGBT in ultra-thin SOI", IEEE EDL, Vol. 18, pp. 414-416, 1997.
    • (1997) IEEE EDL , vol.18 , pp. 414-416
    • Leung, Y.-K.1
  • 15
    • 0035716659 scopus 로고    scopus 로고
    • Localized heating effects and scaling of sub-0.18 micron CMOS devices
    • E. Pop et al., "Localized heating effects and scaling of sub-0.18 micron CMOS devices," IEDM, 2001, pp. 677-680.
    • (2001) IEDM , pp. 677-680
    • Pop, E.1
  • 16
    • 0033710863 scopus 로고    scopus 로고
    • Sub-continuum thermal simulations of deep sub-micron devices under ESD conditions
    • P. G. Sverdrup et al., "Sub-continuum thermal simulations of deep sub-micron devices under ESD conditions," SISPAD, 2000, pp. 54-57.
    • (2000) SISPAD , pp. 54-57
    • Sverdrup, P.G.1
  • 19
    • 0036610426 scopus 로고    scopus 로고
    • Measurement of the effect of self-heating in strained-silicon MOSFETS
    • K. A. Jenkins and K. Rim, "Measurement of the effect of self-heating in strained-silicon MOSFETS", IEEE EDL, Vol. 23, pp. 360-362, 2002.
    • (2002) IEEE EDL , vol.23 , pp. 360-362
    • Jenkins, K.A.1    Rim, K.2
  • 21
    • 20344382295 scopus 로고    scopus 로고
    • Thermal conductivity of ultra-thin single crystal silicon layers, part I - Experimental measurements at room and cryogenic temperatures
    • W. Liu and M. Asheghi, "Thermal conductivity of ultra-thin single crystal silicon layers, part I - experimental measurements at room and cryogenic temperatures," J. Heat Transfer, 2004.
    • (2004) J. Heat Transfer
    • Liu, W.1    Asheghi, M.2
  • 22
    • 0842309721 scopus 로고    scopus 로고
    • Thermal analysis of ultra-thin body device scaling
    • E. Pop et al, "Thermal analysis of ultra-thin body device scaling", IEDM, 2003, pp.883-886.
    • (2003) IEDM , pp. 883-886
    • Pop, E.1
  • 23
    • 0037091483 scopus 로고    scopus 로고
    • Thermal conduction in doped single-crystal silicon films
    • M. Asheghi et al., "Thermal conduction in doped single-crystal silicon films," JAP, Vol. 91, pp. 5079-5088, 2002.
    • (2002) JAP , vol.91 , pp. 5079-5088
    • Asheghi, M.1
  • 24
    • 0001187605 scopus 로고    scopus 로고
    • Concurrent thermal and electrical modeling of sub-micrometer silicon devices
    • J. Lai and A. Majumdar, "Concurrent thermal and electrical modeling of sub-micrometer silicon devices," JAP, Vol. 79, pp. 7353-7363, 1996.
    • (1996) JAP , vol.79 , pp. 7353-7363
    • Lai, J.1    Majumdar, A.2
  • 25
    • 4444351507 scopus 로고    scopus 로고
    • Analytic band Monte Carlo model for electron transport in Si including acoustic and optical phonon dispersion
    • E. Pop et al., "Analytic band Monte Carlo model for electron transport in Si including acoustic and optical phonon dispersion," JAP, 96, 4998, 2004.
    • (2004) JAP , vol.96 , pp. 4998
    • Pop, E.1
  • 26
    • 33748591499 scopus 로고    scopus 로고
    • A split-flux model for phonon transport near hotspots
    • S Sinha et al., "A split-flux model for phonon transport near hotspots", J. Heat Transfer, 2005.
    • (2005) J. Heat Transfer
    • Sinha, S.1
  • 27
    • 33748615339 scopus 로고    scopus 로고
    • Scaling analysis of multilevel interconnect temperatures for high performance ICs
    • in press
    • S. Im et al., "Scaling analysis of multilevel interconnect temperatures for high performance ICs", IEEE TED, 2005 (in press).
    • (2005) IEEE TED
    • Im, S.1
  • 28
    • 33644958333 scopus 로고    scopus 로고
    • A comparative scaling analysis of metallic and carbon nanotube interconnections for nanometer scale VLSI technologies
    • N. Srivastava and K. Banerjee, "A comparative scaling analysis of metallic and carbon nanotube interconnections for nanometer scale VLSI technologies," VMIC, 2004, pp. 393-398.
    • (2004) VMIC , pp. 393-398
    • Srivastava, N.1    Banerjee, K.2
  • 29
    • 0036866915 scopus 로고    scopus 로고
    • A power-optimal repeater insertion methodology for global interconnects in nanometer designs
    • K. Banerjee and A. Mehrotra, "A power-optimal repeater insertion methodology for global interconnects in nanometer designs," IEEE TED, Vol. 49, pp. 2001-2007, 2002.
    • (2002) IEEE TED , vol.49 , pp. 2001-2007
    • Banerjee, K.1    Mehrotra, A.2
  • 30
    • 28444480744 scopus 로고    scopus 로고
    • A probabilistic framework for power-optimal repeater insertion for global interconnects under parameter variations
    • V. Wason and K. Banerjee, "A probabilistic framework for power-optimal repeater insertion for global interconnects under parameter variations," ISLPED, 2005, pp. 131-136.
    • (2005) ISLPED , pp. 131-136
    • Wason, V.1    Banerjee, K.2
  • 31
    • 0034452632 scopus 로고    scopus 로고
    • Full chip thermal analysis of planar (2-D) and vertically integrated (3-D) high performance ICs
    • S. Im and K. Banerjee, "Full chip thermal analysis of planar (2-D) and vertically integrated (3-D) high performance ICs," IEDM, 2000, pp. 727-730.
    • (2000) IEDM , pp. 727-730
    • Im, S.1    Banerjee, K.2
  • 32
    • 84950148025 scopus 로고    scopus 로고
    • Full chip thermal simulation
    • Z. Yu et al., "Full chip thermal simulation," ISQED, 2000, pp.145-149.
    • (2000) ISQED , pp. 145-149
    • Yu, Z.1
  • 33
    • 0033712192 scopus 로고    scopus 로고
    • Dynamic power management of complex systems using generalized stochastic Petri nets
    • Q. Wu, Q. Qiu, and M. Pedram, "Dynamic power management of complex systems using generalized stochastic Petri nets," DAC, 2000, pp. 352-356.
    • (2000) DAC , pp. 352-356
    • Wu, Q.1    Qiu, Q.2    Pedram, M.3
  • 35
    • 0035212298 scopus 로고    scopus 로고
    • Analysis of substrate thermal gradient effects on optimal buffer insertion
    • A. H. Ajami, K. Banerjee and M. Pedram, "Analysis of substrate thermal gradient effects on optimal buffer insertion", ICCAD, 2001, pp. 44-48.
    • (2001) ICCAD , pp. 44-48
    • Ajami, A.H.1    Banerjee, K.2    Pedram, M.3
  • 36
    • 29644444436 scopus 로고    scopus 로고
    • A self-consistent junction temperature estimation methodology for nanometer scale ICs with implications for performance and thermal management
    • K. Banerjee et al., "A self-consistent junction temperature estimation methodology for nanometer scale ICs with implications for performance and thermal management," IEDM, 2003, pp. 893-896.
    • (2003) IEDM , pp. 893-896
    • Banerjee, K.1
  • 37
    • 0028736474 scopus 로고
    • Low power digital design
    • M. Horowitz et al., "Low power digital design," ISLPED, 1994, pp. 8-11.
    • (1994) ISLPED , pp. 8-11
    • Horowitz, M.1
  • 38
    • 33748542268 scopus 로고    scopus 로고
    • A thermally aware methodology for design-specific optimization of supply and threshold voltages in nanometer scale ICs
    • S-C. Lin et al., "A thermally aware methodology for design-specific optimization of supply and threshold voltages in nanometer scale ICs," ICCD, 2005, pp. 411-416.
    • (2005) ICCD , pp. 411-416
    • Lin, S.-C.1
  • 39
    • 84991935560 scopus 로고    scopus 로고
    • Energy-delay efficiency of VLSI computations
    • P. I. Pénzes and A. J. Martin, "Energy-delay efficiency of VLSI computations," GLSVLSI, 2002, pp. 104-111.
    • (2002) GLSVLSI , pp. 104-111
    • Pénzes, P.I.1    Martin, A.J.2
  • 40
    • 0036395317 scopus 로고    scopus 로고
    • Power-constrained microprocessor design
    • H. P. Hofstee, "Power-constrained microprocessor design," ICCD, 2002, pp. 14-16.
    • (2002) ICCD , pp. 14-16
    • Hofstee, H.P.1
  • 41
    • 0041633858 scopus 로고    scopus 로고
    • Parameter variations and impact on circuits and microarchitecture
    • S. Borkar et al., "Parameter variations and impact on circuits and microarchitecture," DAC, 2003, pp. 338-342.
    • (2003) DAC , pp. 338-342
    • Borkar, S.1
  • 42
    • 0032592096 scopus 로고    scopus 로고
    • Design challenges of technology scaling
    • S. Borkar, "Design challenges of technology scaling," IEEE Micro, Vol. 19, pp. 23-29, 1999.
    • (1999) IEEE Micro , vol.19 , pp. 23-29
    • Borkar, S.1
  • 43
    • 16244421701 scopus 로고    scopus 로고
    • A probabilistic framework to estimate full-chip subthreshold leakage power distribution considering within-die and die-to-die P-T-V variations
    • S. Zhang et al., "A probabilistic framework to estimate full-chip subthreshold leakage power distribution considering within-die and die-to-die P-T-V variations," ISLPED, 2004, pp. 156-161.
    • (2004) ISLPED , pp. 156-161
    • Zhang, S.1
  • 44
    • 0032314375 scopus 로고    scopus 로고
    • Control of off-state current in scaled PD/SOI CMOS digital circuits
    • M.M. Pelella, J.G. Fossum, and S. Krishnan, "Control of off-state current in scaled PD/SOI CMOS digital circuits," International SOI conference, 1998, pp. 147-148.
    • (1998) International SOI Conference , pp. 147-148
    • Pelella, M.M.1    Fossum, J.G.2    Krishnan, S.3
  • 45
    • 34547159207 scopus 로고    scopus 로고
    • Analysis and implications of 1C cooling for deep nanometer scale CMOS technologies
    • to appear
    • S-C. Lin et al., "Analysis and implications of 1C cooling for deep nanometer scale CMOS technologies", IEDM, 2005 (to appear).
    • (2005) IEDM
    • Lin, S.-C.1
  • 46
    • 33747566850 scopus 로고    scopus 로고
    • 3-D ICs: A novel chip design for improving deep submicron interconnect performance and systems-on-chip integration
    • K. Banerjee, et al, "3-D ICs: A novel chip design for improving deep submicron interconnect performance and systems-on-chip integration," Proceedings of the IEEE, Vol. 89, pp. 602-633, 2001.
    • (2001) Proceedings of the IEEE , vol.89 , pp. 602-633
    • Banerjee, K.1
  • 47
    • 33748630936 scopus 로고    scopus 로고
    • Performance analysis of carbon nanotube interconnects for VLSI applications
    • N. Srivastava and K. Banerjee, "Performance analysis of carbon nanotube interconnects for VLSI applications", ICCAD, 2005, pp. 383-390.
    • (2005) ICCAD , pp. 383-390
    • Srivastava, N.1    Banerjee, K.2
  • 48
    • 33750340818 scopus 로고    scopus 로고
    • Carbon nanotube interconnects: Implications for performance, power dissipation and thermal management
    • to appear
    • N. Srivastava, R. V. Joshi and K. Banerjee, "Carbon nanotube interconnects: implications for performance, power dissipation and thermal management", IEDM, 2005 (to appear).
    • (2005) IEDM
    • Srivastava, N.1    Joshi, R.V.2    Banerjee, K.3


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