A thermally-aware methodology for design-specific optimization of supply and threshold voltages in nanometer scale ICs

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn 2005, Issue , 2005, Pages 411-416

  Lin, Sheng Chih ^a   Srivastava, Navin ^a   Banerjee, Kaustav ^a  

^a University of California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP TEMPERATURE; ELECTROTHERMAL EFFECTS; LEAKAGE POWER; NANOMETERS;

ELECTRIC NETWORK ANALYSIS; MICROPROCESSOR CHIPS; OPTIMIZATION; POWER CONTROL; POWER SUPPLY CIRCUITS; THRESHOLD VOLTAGE; VLSI CIRCUITS;

CMOS INTEGRATED CIRCUITS;

EID: 33748542268     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2005.16     Document Type: Conference Paper

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