Full chip thermal simulation

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2000-January, Issue , 2000, Pages 145-149

  Yu, Zhiping ^a,c   Yergeau, Dan ^a   Dutton, Robert W ^a   Nakagawa, Sam ^b   Chang, Norman ^b   Lin, Shen ^b   Xie, Weize ^b  

^a Stanford University   (United States)

^b HEWLETT PACKARD COMPANY   (United States)

^c HP ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN; INTEGRATED CIRCUIT INTERCONNECTS; TEMPERATURE DISTRIBUTION; THERMOANALYSIS;

ELECTRICAL SIMULATION; FULL-CHIP THERMAL ANALYSIS; INTERCONNECT LAYERS; OPERATIONAL TEMPERATURE; SIMULATED STRUCTURE; SURROUNDING ENVIRONMENT; THERMAL DIFFUSION EQUATIONS; THERMAL SIMULATIONS;

THERMAL CONDUCTIVITY;

EID: 84950148025     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2000.838867     Document Type: Conference Paper

References (3)

1. B. H. Krabbenborg, A. Bosma, H. C. de Graaff, and A. J. Mouthaan, "Layout to circuit extraction for three-dimensional thermal-electrical circuit simulation of device structure", IEEE Tr. CAD IC and S, Vol. 15, No. 7, p. 765, July 1996.
2. E. Leobandung, et al., "Scalability of SOI technology into 0.13μm 1.2V CMOS generation", IEDM'98 p. 403, San Francisco, Dec. 1998.
3. C. S. Rafferty, Z. Yu, B. Biegel, M. G. Ancona, J. Bude, and R. W. Dutton, "Multi-dimensional quantum effect simulation using a density-gradient model and script-level programming techniques", SISPAD'98 p. 137, Lueven, Belgium, Sept. 1998.