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Volumn 2006, Issue , 2006, Pages 1-23

Rapid VLIW processor customization for signal processing applications using combinational hardware functions

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN AUTOMATION; HARDWARE FUNCTIONS; MULTIPLIERS; SOFTWARE KERNELS;

EID: 33645690156     PISSN: 11108657     EISSN: None     Source Type: Journal    
DOI: 10.1155/ASP/2006/46472     Document Type: Article
Times cited : (21)

References (61)
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    • A practical approach to hardware and software SoC tradeoffs using high-level synthesis for architectural exploration
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    • Pursley, D.J.1    Cline, B.L.2
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    • I. Ghosh M. Fujita Automatic test pattern generation for functional RTL circuits using assignment decision diagrams. Proceedings of 37th Design Automation Conference (DAC '00) Los Angeles, Calif, USA 2000 43 48
    • (2000) Proceedings of 37th Design Automation Conference (DAC '00) , pp. 43-48
    • Ghosh, I.1    Fujita, M.2
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    • 0141958010 scopus 로고    scopus 로고
    • Scalar coprocessors for accelerating the G723.1 and G729A speech coders
    • V. A. Chouliaras J. Nunez Scalar coprocessors for accelerating the G723.1 and G729A speech coders. IEEE Transactions on Consumer Electronics 49 2003 3 703 710
    • (2003) IEEE Transactions on Consumer Electronics , vol.49 , Issue.3 , pp. 703-710
    • Chouliaras, V.A.1    Nunez, J.2
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    • 44.6\% processing cycles reduction in GSM voice coding by low-power reconfigurable co-processor architecture
    • E. Atzori S. M. Carta L. Raffo 44.6\% processing cycles reduction in GSM voice coding by low-power reconfigurable co-processor architecture. IEE Electronics Letters 38 2002 24 1524 1526
    • (2002) IEE Electronics Letters , vol.38 , Issue.24 , pp. 1524-1526
    • Atzori, E.1    Carta, S.M.2    Raffo, L.3
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    • 0030394522 scopus 로고    scopus 로고
    • MATRIX: A reconfigurable computing architecture with configurable instruction distribution and deployable resources
    • Napa Valley, Calif, USA
    • E. Mirsky A. DeHon MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources. Proceedings of 4th IEEE Symposium on FPGAs for Custom Computing Machines (FCCM '96) Napa Valley, Calif, USA 1996 157 166
    • (1996) Proceedings of 4th IEEE Symposium on FPGAs for Custom Computing Machines (FCCM '96) , pp. 157-166
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    • Imagine: Media processing with streams
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    • T. J. Callahan J. R. Hauser J. Wawrzynek The Garp architecture and C compiler. Computer 33 2000 4 62 69
    • (2000) Computer , vol.33 , Issue.4 , pp. 62-69
    • Callahan, T.J.1    Hauser, J.R.2    Wawrzynek, J.3
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.