An enhanced floating point coprocessor for embedded signal processing and graphics applications

Conference Record of the 33rd Asilomar Conference on Signals, Systems, and Computers

Volumn 1, Issue , 1999, Pages 147-151

  Hinds, Chris N ^a  

^a ARM Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COPROCESSOR; DIGITAL ARITHMETIC; IMAGE COMPRESSION; PIPELINE PROCESSING SYSTEMS; SIGNAL PROCESSING; SPEECH RECOGNITION; ALGORITHMS; MICROPROCESSOR CHIPS;

ARITHMETIC INSTRUCTIONS; EMBEDDED SIGNAL PROCESSING; FLOATING POINTS; FLOATING-POINT MULTIPLY-ACCUMULATE; GENERAL-PURPOSE MICROPROCESSORS; GRAPHICS APPLICATIONS; PARALLEL PROCESSING; RECOGNITION ALGORITHM;

COMPUTER ARCHITECTURE; DIGITAL SIGNAL PROCESSING;

FLOATING POINT COPROCESSOR;

EID: 0033348139     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ACSSC.1999.832312     Document Type: Conference Paper

References (5)

1. "IEEE Standard for Binary Floating-point Arithmetic, " ANSI/IEEE Standard No. 754-1985, The Institute of Electrical and Electronics Engineers, Inc., New York, New York, 10017.
2. P. Lapsley, J. Bier, A. Shohan, E. Lee, DSP Processor Fundamentals, IEEE Press, New York, New York, 1997.
3. R. K. Montoye, E. Hokenek. and S. L. Runyon, "Design of the IBM RISC Systeml6000 floating-point execution unit, " IBM J. Res. Develop. 34, 59-70, 1990.
4. W. Kahan, Contracted Multiply-Adds, monograph, Dept. of Computer Science, University of California, Berkeley, 1991.
5. D. Jaggar. Advanced RISC Machines Architectural Reference Mannual, Prentice Hall, London, 1996.