Overview of a Compiler for Synthesizing MATLAB Programs onto FPGAs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 12, Issue 3, 2004, Pages 312-324

  Banerjee, Prithviraj ^a   Haldar, Malay ^b,c   Nayak, Anshuman ^b,d   Kim, Victor ^b,c   Saxena, Vikram ^b,e   Parkes, Steven ^b,f   Bagchi, Debabrata ^b,d   Pal, Satrajit ^b,d   Tripathi, Nikhil ^b,d   Zaretsky, David ^a,b   Anderson, Robert ^b   Uribe, Juan Ramon ^b  

^a Northwestern University   (United States)

^b AccelChip Inc   (United States)

^c Calypto Design Systems   (United States)

^d Atrenta   (India)

^e SYNOPSYS INC   (United States)

^f IBM ALMADEN RESEARCH CENTER   (United States)

Author keywords

Field programmable gate arrays (FPGAs); High level synthesis; MATLAB; Register transfer level (RTL); Verilog; VHDL

Indexed keywords

CODES (SYMBOLS); COMPUTER ARCHITECTURE; COMPUTER PROGRAMMING LANGUAGES; COMPUTER SIMULATION; DIGITAL SIGNAL PROCESSING; LOGIC DESIGN; OBJECT ORIENTED PROGRAMMING; PROGRAM COMPILERS;

HIGH-LEVEL SYNTHESIS; MATLAB; REGISTER TRANSFER LEVELS (RTL); VERILOG; VHDL;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 11144356537     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.824301     Document Type: Conference Paper

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