The imagine stream processor

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2002, Pages 282-288

  Kapasi, Ujval J ^a   Dally, William J ^a   Rixner, Scott ^a   Owens, John D ^a   Khailany, Brucek ^a  

^a RICE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

C (PROGRAMMING LANGUAGE); CMOS INTEGRATED CIRCUITS; COMPUTER PROGRAMMING; COMPUTER SIMULATION; DIGITAL ARITHMETIC; DYNAMIC RANDOM ACCESS STORAGE; FAST FOURIER TRANSFORMS; FIELD PROGRAMMABLE GATE ARRAYS; MULTIMEDIA SYSTEMS; PARALLEL PROCESSING SYSTEMS; PROGRAM COMPILERS; VERY LONG INSTRUCTION WORD ARCHITECTURE;

ARITHMETIC LOGIC UNITS; IMAGINE STREAM PROCESSOR; PROGRAMMABLE MEDIA PROCESSOR; STREAM PROGRAMMING MODEL;

MICROPROCESSOR CHIPS;

EID: 0036396915     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

1. E. Caspi, A. Dehon, and J. Wawrzynek. A Streaming Multi-threaded Model. In Proceedings of the Third Workshop on Media and Stream Processors, pages 21-28, Austin, TX. Dec 2001.
2. W. J. Dally, P. Hanrahan, and R. Fedkiw. A Streaming Supercomputer. Stanford Computer Systems Laboratory White Paper, September 2001.
3. T. Kanade, A. Yoshida, K. Oda, H. Kano, and M. Tanaka. A Stereo Machine for Video-rate Dense Depth Mapping and its New Applications. In Proceedings of the 15th Computer Vision and Pattern Recognition Conference, pages 196-202, June 1996.
4. U. J. Kapasi, W. J. Dally, S. Rixner, P. R. Mattson, J. D. Owens, and B. Khailany. Efficient Conditional Operations for Data-parallel Architectures. In Proceedings of the 33rd IEEE/ACM International Symposium on Microarchitecture, pages 159-170, December 2000.
5. U. J. Kapasi, P. Mattson, W. J. Dally, J. D. Owens, and B. Towles. Stream Scheduling. Concurrent VLSI Architecture Tech Report 122. Stanford University, Computer Systems Laboratory, March 2002.
6. B. Khailany, W. J. Dally, U. J. Kapasi, P. Mattson, J. Namkoong, J. D. Owens, B. Towles, A. Chang, and S. Rixner. Imagine: Media Processing with Streams. IEEE Micro, pages 35-46, Mar/Apr 2001.
7. P. Mattson, W. J. Dally, S. Rixner, U. J. Kapasi, and J. D. Owens. Communication Scheduling. In Proceedings of the 9th International Conference on Architectural Support for Programming Languages and Operating Systems, November 2000.
8. J. D. Owens, W. J. Dally, U. J. Kapasi, S. Rixner, P. Mattson, and B. Mowery. Polygon Rendering on a Stream Architecture. In Proceedings of the 2000 SIGGRAPH / Eurographics Workshop on Graphics Hardware, pages 23-32, August 2000.
9. M. C. Pease. An Adaptation of the Fast Fourier Transform for Parallel Processing. Journal of the ACM, 15(2):252-264, April 1968.
10. S. Rixner, Stream Processor Architecture. Kluwer Academic Publishers, Boston, MA, 2001.
11. S. Rixner, W. J. Dally, B. Khailany, P. R. Mattson, U. J. Kapasi, and J. D. Owens. Register Organization for Media Processing. In Proceedings of the 6th International Symposium on High-Performance Computer Architecture, pages 375-386, January 2000.
12. R. Russell. The Cray-1 Computer System. Comm. ACM, 21(1):63-72, Jan 1978.
13. M. B. Taylor and et al. The Raw Microprocessor: A Computational Fabric for Software Circuits and General Purpose Programs. IEEE Micro, Mar/Apr 2002.
14. J. V. M. Bove and J. A. Watlington. Cheops: A Reconfigurable Data-flow System for Video Processing. IEEE Trans. on Circuits and Systems for Video Tech., pages 140-149, April 5 1995.