Specifying and compiling applications for RaPiD

Proceedings - IEEE Symposium on FPGAs for Custom Computing Machines, FCCM 1998

Volumn 1998-April, Issue , 1998, Pages 116-125

  Cronquist, D C ^a   Franklin, P ^a   Berg, S G ^a   Ebeling, C ^a  

^a University of Washington   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTERS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HIGH LEVEL LANGUAGES; MEMORY ARCHITECTURE; PROGRAM COMPILERS; RECONFIGURABLE ARCHITECTURES;

COMPUTATION INTENSIVES; CONTROL CIRCUITRY; DATA-PATH ARCHITECTURE; DYNAMIC CONTROLS; FLEXIBLE ARCHITECTURES; PIPELINED COMPUTATION; PIPELINED IMPLEMENTATION; SPECIAL PURPOSE HARDWARE;

PIPELINES;

EID: 85013779657     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPGA.1998.707889     Document Type: Conference Paper

References (5)

1. C. Ebeling, D. C. Cronquist, and P. Franklin. RaPiD|reconfigurable pipelined datapath. In R. Hartenstein and M. Glesner, editors, 6th International Workshop on Field-Programmable Logic and Compilers, Lecture Notes in Computer Science, pages 126-135. Springer-Verlag, September 1996.
2. C. Ebeling, D. C. Cronquist, P. Franklin, and S. Berg. Mapping applications to the rapid configurable architecture. In Field-Programmable Custom Computing Machines (FCCM-97), 1997.
3. P. Lee and Z. M. Kedem. On high-speed computing with a programmable linear array. In Proceedings. Supercomputing '88, pages 425-32. IEEE Comput. Soc. Press, 1988.
4. D. Moldovan and J. A. B. Fortes. Partitioning and mapping algorithms into fixed size systolic arrays. IEEE Transactions on Computers, C-35(1):1-12, 1986.
5. M. E. Wolf and M. S. Lam. A loop transformation theory and an algorithm to maximize parallelism. IEEE Transactions on Parallel and Distributed Systems, 2(4):452-471, 1991.