Efficient Sequential ATPG for Functional RTL Circuits

IEEE International Test Conference (TC)

Volumn , Issue , 2003, Pages 290-298

  Zhang, Liang ^a   Ghosh, Indradeep ^b   Hsiao, Michael ^a  

^a State University   (United States)

^b FUJITSU LABORATORIES OF AMERICA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; GENETIC ALGORITHMS; GRAPH THEORY; TRANSISTORS;

STATIC LEARNING;

AUTOMATIC TESTING;

EID: 0242303066     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

1. A. R. N. Abhijit Ghosh, Srinivas Devadas. Sequential test generation and synthesis for testability at the register-transfer and logic levels. IEEE Trans. Computer-Aided Design, 12(5):579-588, May 1993.
2. V. Chaiyakul, D. D. Gajski, and L. Ramachandran. High-level transformations for minimizing syntactic variances. In Proc. Design Automation Conf., pages 413-418, June 1993.
3. F. Corno, M. S. Reorda, and G. Squillero. RT-Level ITC'99 benchmarks and first ATPG results. IEEE Design & Test of Computers, 17(3):44-53, July-September 2000.
4. H.-K. T. Devadas, A. R. Newton, and A. Sangiovannivincentelli. Test generation for sequential circuits. IEEE Trans. Computer-Aided Design, 7(10):1081-1093, October 1988.
5. F. Fallah, S. Devadas, and K. Keutzer. OCCOM - Efficient computation of observability-based code coverage metrics for functional verification. IEEE Trans. Computer-Aided Design, 20(8): 1003-1015, August 2001.
6. F.Corno, G.Cumani, M. Reorda, and G.Squillero. Effective techniques for high-level ATPG. In Proc. IEEE Asian Test Symposium, pages 225-230, 2001.
7. F. Ferrandi, F. Fummi, and D. Sciuto. Implicit test generation for behavioral VHDL models. In Proc. International Test Conference, pages 436-441, 1998.
8. I. Ghosh and M. Fujita. Automatic test pattern generation for functional register-transfer level circuits using assignment decision diagrams. IEEE Trans. Computer-Aided Design, 20(3):402-415, March 2001.
9. R. Guo, S. Reddy, and I. Pomeranz. PROPTEST: a property based test pattern generator for sequential circuits using test compaction. In Proc. Design Automation Conference, pages 653-659, 1999.
10. M. Hsiao, E. Rudnick, and J. Patel. Sequential circuit test generation using dynamic state traversal. In Proc. Eur. Design Test Conf., pages 22-28, Mar 1997.
11. T. Niermann and J. Patel. HITEC: A test generation package for sequential circuits. In Proc. Eur. Design Automation Conf., pages 214-218, Feb. 1991.
12. S. Ravi, G.Lakshminarayana, and N.K.Jha. TAO: Regular expression based high-level testability analysis and optimization,. In Proc. Int. Test Conf., pages 331-340, 1998.
13. S. Ravi and N. Jha. Fast test generation for circuits with RTL and gate-level views. In Proc. International Test Conference, pages 1068-1077, 2001.
14. E. M. Rudnick, R. Vietti, and et al. Fast sequential circuit test generation using high-level and gate-level techniques. In Proc. Design Automation and Test in Europe, pages 570-576, 1998.