Profiling tools for hardware/software partitioning of embedded applications

Proceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)

Volumn , Issue , 2003, Pages 189-198

  Suresh, Dinesh C ^a   Najjar, Walid A ^a   Vahid, Frank ^a   Villarreal, Jason R ^a   Stitt, Greg ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Compiler optimization; Hardware software partitioning; Loop analysis

Indexed keywords

EMBEDDED SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS; MICROPROCESSOR CHIPS; OPTIMIZATION; PROGRAM COMPILERS; SUPERVISORY AND EXECUTIVE PROGRAMS;

HARDWARE PARTITIONING; LOOP PROFILING; SOFTWARE PARTITIONING;

COMPUTER SYSTEMS PROGRAMMING;

EID: 0242443861     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/780732.780759     Document Type: Conference Paper

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