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Volumn , Issue , 1999, Pages 23-40

Architecture design of reconfigurable pipelined datapaths

Author keywords

[No Author keywords available]

Indexed keywords

EMBEDDED SYSTEMS; GENERAL PURPOSE COMPUTERS; SIGNAL PROCESSING; VLSI CIRCUITS;

EID: 84966670525     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ARVLSI.1999.756035     Document Type: Conference Paper
Times cited : (102)

References (11)
  • 4
    • 0029386906 scopus 로고
    • Mapping real-time motion estimation type algorithms to memory Efficient, programmable multiprocessor architectures
    • E. De Greef, F. Catthoor, and H. De Man. Mapping real-time motion estimation type algorithms to memory Efficient, programmable multiprocessor architectures. Microprocessing & Microprogramming, 41(5-6):409-23, 1995.
    • (1995) Microprocessing & Microprogramming , vol.41 , Issue.5-6 , pp. 409-423
    • De Greef, E.1    Catthoor, F.2    De Man, H.3
  • 6
    • 0041996562 scopus 로고
    • Let's design algorithms for VLSI systems
    • Carnegie-Mellon University, January
    • H. T. Kung. Let's design algorithms for VLSI systems. Technical Report CMU-CS-79-151, Carnegie-Mellon University, January 1979.
    • (1979) Technical Report CMU-CS-79-151
    • Kung, H.T.1
  • 8
    • 0024143306 scopus 로고
    • Synthesizing linear array algorithms from nested for loop algorithms
    • P. Lee and Z. M. Kedem. Synthesizing linear array algorithms from nested FOR loop algorithms. IEEE Transactions on Computers, 37(12):1578-98, 1988.
    • (1988) IEEE Transactions on Computers , vol.37 , Issue.12 , pp. 1578-1598
    • Lee, P.1    Kedem, Z.M.2
  • 9
    • 33746763910 scopus 로고
    • Retiming synchronous circuitry
    • Charles E. Leiserson and James B. Saxe. Retiming synchronous circuitry. Algorithmica, 6:5-35, 1991.
    • (1991) Algorithmica , vol.6 , pp. 5-35
    • Leiserson, C.E.1    Saxe, J.B.2
  • 10
    • 0022482205 scopus 로고
    • Partitioning and mapping algorithms into fixed size systolic arrays
    • D. I. Moldovan and J. A. B. Fortes. Partitioning and mapping algorithms into fixed size systolic arrays. IEEE Transactions on Computers, C-35(1):1-12, 1986.
    • (1986) IEEE Transactions on Computers , vol.C-35 , Issue.1 , pp. 1-12
    • Moldovan, D.I.1    Fortes, J.A.B.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.