DC performance of deep submicrometer Schottky-gated n-channel Si:SiGe HFETs at low temperatures

IEEE Transactions on Electron Devices

Volumn 52, Issue 9, 2005, Pages 2067-2074

  Gaspari, V ^a   Fobelets, K ^a   Velazquez Perez, J E ^b   Hackbarth, T ^c  

^a IMPERIAL COLLEGE LONDON   (United Kingdom)

^b UNIVERSITY OF SALAMANCA   (Spain)

^c DAIMLER AG   (Germany)

Author keywords

Kink effect; Low temperature; MODFET; SiGe

Indexed keywords

ELECTRIC FIELD EFFECTS; HETEROJUNCTIONS; IMPACT IONIZATION; LEAKAGE CURRENTS; SEMICONDUCTING SILICON COMPOUNDS; THERMAL EFFECTS; TRANSCONDUCTANCE;

HETEROSTRUCTURE FIELD-EFFECT TRANSISTORS; KINK EFFECT; SEMICONDUCTING SILICON GERMANIUM;

MESFET DEVICES;

EID: 26244460338     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2005.855059     Document Type: Article

References (37)

1. J. Welser, J. L. Hoyt, and J. F. Gibbons, "Electron-mobility enhancement in strained-Si n-type metal-oxide-semiconductor field-effect transistors," IEEE Trans. Electron Devices, vol. 15, no. 3, p. 100, Mar. 1994.
2. F. Schäffler, "High-mobility Si and Ge structures," Semicond Sci. Technol., vol. 12, p. 1515, 1997.
3. V. Gaspari, K. Fobelets, P. W. Ding, J. E. Velazquez-Perez, S. H. Olsen, A. G. O'Neill, and J. Zhang, "Temperature dependence of sub-micrometer strained-Si surface channel n-type MOSFETs in dynamic-threshold mode," IEEE Electron Device Lett., vol. 25, no. 5, p. 334, May 2004.
4. V. Gaspari, K. Fobelets, J. E. Velazquez-Perez, R. Ferguson, K. Michelakis, S. Despotopoulos, and C. Papavassilliou, "Effect of temperature on the transfer characteristic of a 0.5 μm-gate Si:SiGe depletion-mode n-MODFET," Appl. Surf. Sci., vol. 224, p. 390, 2004.
5. S. H. Olsen, A. G. O'Neill, L. S. Driscoll, K. S. K. Kwa, S. Chattopadhyay, A. M. Waite, Y. T. Tang, A. G. R. Evans, D. J. Norris, A. G. Cullis, D. J. Paul, and D. J. Robbins, "High-performance nMOSFETs using a novel strained Si/SiGe CMOS architecture," IEEE Trans. Electron Devices, vol. 50, no. 9, p. 1961, Sep. 2003.
6. K. Michelakis, S. Despotopoulos, V. Gaspari, A. Vilches, K. Fobelets, C. Papavassilliou, and C. Toumazou, "SiGe virtual substrate HMOS transistor for analogue applications," Appl. Surf. Sci., vol. 224, no. 1-4, p. 386, 2004.
7. 0.45 n-MODFETs," IEEE Trans. Electron Devices, vol. 47, no. 7, p. 1477, Jul. 2000.
8. A. Vilches, K. Michelakis, K. Fobelets, D. Haigh, C. Papavassiliou, T. Hackbarth, and U. König, "Buried-channel SiGe HMODFET device potential for micropower Applications," Solid State Electron., vol. 48, no. 8, p. 1423, 2004.
9. K. Fobelets, W. Jeamsaksiri, C. Papavasilliou, A. Vilches, V. Gaspari, J. E. Velazquez-Perez, K. Michelakis, T. Hackbarth, and U. König, "Comparison of sub-micron Si: SiGe heterojunction nFETs to Si nMOSFET in present-day technologies," Solid State Electron., vol. 48, no. 8, p. 1401, 2004.
10. F. Balestra and G. Ghibaude, Device and Circuit Cryogenic Operation for Low Temperature Electronics. Norwell, MA: Kluwer, 2001.
11. V. Gaspari, K. Fobelets, J. E. Velazquez-Perez, M. J. Prest, and T. E. Whall, "Dynamic threshold mode operation of p-channel Si and strained-SiGe MOSFETs between 10 K and 300 K," Semicond. Sci. Technol., vol. 19, p. L95, 2004.
12. N. Sugii and K. Washio, "Low-temperature electrical characteristics of strained-Si MOSFETs," Jpn. J. Appl. Phys., vol. 42, p. 1924, 2003.
13. M. Shur, Physics of Semiconductor Devices. Englewood Cliffs, NJ: Prentice-Hall, 1990.
14. S. Selberherr, Analysis and Simulation of Semiconductor Devices. Berlin, Germany: Springer-Verlag, 1984.
15. Y. Tsividis, Operation and Modeling of the MOS Transistor, 2nd ed. New York: McGraw-Hill, 1999, sec. 4.6.
16. T. Takagi, A. Inoue, Y. Hara, Y. Kanzana, and M. Kubo, "A novel high performance SiGe channel heterostructure dynamic threshold pMOSFET (HDTMOS)," IEEE Electron Device Lett., vol. 22, no. 5, p. 206, May 2001.
17. S. M. Sze, Physics of Semiconductor Devices, 2nd ed: Wiley, 1981, sec. 2.4.
18. Z. M. Li, D. J. Day, S. P. McAlister, and C. M. Hurd, "Subthreshold current in undoped AlGaAs/GaAs MODFET structures," IEEE Trans. Electron Devices, vol. 38, no. 2, p. 207, Feb. 1991.
19. I. M. Hafez, G. Ghibando, and F. Balestra, "Analysis of the kink effect in MOS transistors," IEEE Trans. Electron Devices, vol. 37, no. 3, p. 818, Mar. 1990.
20. L. Deferm, E. Simoen, and C. Claeys, "The importance of the internal bulk-source potential on the low-temperature Kink in NMOSTs," IEEE Trans. Electron Devices, vol. 38, no. 6, p. 1459, 1991.
21. M. H. Somerville, A. Ernst, and J. A. del Alamo, "A physical model for the kink effect in InAlAs/InGaAs HEMTs," IEEE Trans. Electron Devices, vol. 47, no. 5, p. 922, May 2000.
22. I. M. Hafez, G. Ghibando, and F. Baiestra, "Reduction of kink effect in short-channel MOS transistors," IEEE Electron Device Lett., vol. 11, no. 3, p. 120, Mar. 1990.
23. U. König and F. Schäffler, "Si: SiGe modulation doped field-effect transistor with two electron channels," Electron. Lett., vol. 27, no. 16, p. 1405, 1991.
24. B. Bozon, T. Zijlstra, M. Glück, J. Hersener, E. van der Drift, and U. König, "A low temperature gate oxide process for n-channel SiGe modulation doped field effect transistors," J. Appl. Phys., vol. 82, no. 9, p. 4611, 1997.
25. V. Gaspari, K. Fobelets, J. E. Velazquez-Perez, T. Hackbarth, and U. Konig, "Anomalous behavior of buried strained-Si channel Heterojunction FETs at low temperatures," in Proc. Joint Int. Meeting Electrochemical Society/Electrochemical Society Japan, Honolulu, Hawaii, 2004.
26. J. J. Lieu, A. Ortiz-Conde, and F. Garcia-Sanchez, Analysis and Design of MOSFETs: Modeling, Simulation, and Parameter Extraction. Norwell, MA: Kluwer, 1998, ch. 5.
27. T. C. Hsiao, P. Liu, and J. C. S. Woo, "Advanced technologies for optimized sub-quarter-micrometer SOI CMOS devices," IEEE Trans. Electron Devices, vol. 45, no. 5, p. 1092, May 1998
28. C. Wang, J. P. Snyder, and J. R. Tucker, "Sub-40 nm PtSi Schottky source/drain metal-oxide-semiconductor field effect transistors," Appl. Phys. Lett., vol. 74, no. 8, p. 1174, 1999.
29. M. Nishisaka and T. Asano, "Reduction of the floating body effect in SOI MOSFETs by using Schottky source/drain contacts," Jpn. J. Appl. Phys., vol. 37, no. 3B, p. 1295, 1998.
30. S. A. Rishton, K. Ismail, J. O. Chu, and K. Chan, "An MOS transistor with Schottloy source/drain contacts and a self-aligned low-resistance T-gate," Microelect. Eng., vol. 35, p. 361, 1997.
31. S. A. Rishton, K. Ismail, J. O. Chu, K. K. Chan, and K. Y. Lee, "New complimentary metal-oxide semiconductor technology with self-aligned Schottky source/drain and low-resistance T gates," J. Vac. Sci. Technol. B, Microelectron. Process. Phenom., vol. 15, no. 6, p. 2795, 1997.
32. M. Saitoh, A. Itoh, S. Yamagami, and M. Asada, "Analysis of short-channel Schottky source/drain metal-oxide-semiconductor field-effect transistor on silicon-on-insulator substrate and demonstration of sub-50-nm n-type devices with metal gate," Jpn. J. Appl. Phys., vol. 38, no. 11, p. 6226, 1999.
33. A. Itoh, M. Saitoh, and M. Asada, "A 25-nm-long channel metal-gate p-type Schottky source/drain metal-oxide-semiconductor field effect transistor on separation-by-implanted-oxygen substrate," Jpn. J. Appl. Phys., vol. 39, no. 8, p. 4757, 2000.
34. Microsoft Office Excel 2003 Help. [Online] http://office.microsoft.com/ assistance
35. G. S. Gildenblat and C. L. Huang, "N-channel MOSFET model for the 60-300-K temperature range," IEEE Trans. Computer-Aided Des. Integr. Circuits Syst., vol. 10, no. 4, p. 512, 1991.
36. A. Vilches, K. Fobelets, K. Michelakis, S. Despotopoulos, C. Papavassiliou, T. Hackbarth, and U. König, "SiGe HMODFET 'KAIST' micropower model and amplifier realization," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 6, p. 1100, Jun. 2004.
37. I. M. Hafez, F. Balestra, and G. Ghibaudo, "Characterization and modeling of silicon metal-oxide-semiconductor transistors at liquid-helium temperature: influence of source/drain series resistances," J. Appl. Phys., vol. 88, no. 7, p. 3694, 1990.