High-performance nMOSFETs using a novel strained Si/SiGe CMOS architecture

IEEE Transactions on Electron Devices

Volumn 50, Issue 9, 2003, Pages 1961-1969

  Olsen, Sarah H ^a   O'Neill, Anthony G ^a   Driscoll, Luke S ^a   Kwa, Kelvin S K ^a   Chattopadhyay, Sanatan ^a   Waite, Andrew M ^b   Tang, Yue T ^b   Evans, Alan G R ^b   Norris, David J ^c   Cullis, Anthony G ^c   Paul, Douglas J ^d   Robbins, David J ^e  

^a NEWCASTLE UNIVERSITY   (United Kingdom)

^b UNIVERSITY OF SOUTHAMPTON   (United Kingdom)

^c UNIVERSITY OF SHEFFIELD   (United Kingdom)

^d UNIVERSITY OF CAMBRIDGE   (United Kingdom)

^e QINETIQ   (United Kingdom)

Author keywords

CMOS; Drain current enhancement; nMOSFETs; Self heating; SiGe; Strained silicon; Thermal budget; Transconductance enhancement; Virtual substrate

Indexed keywords

CHEMICAL MECHANICAL POLISHING; CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENTS; SEMICONDUCTING SILICON COMPOUNDS; SEMICONDUCTOR DEVICE MANUFACTURE; TRANSCONDUCTANCE;

FIELD EFFECT MOBILITY; THERMAL BUDGET PROCESS; VIRTUAL SUBSTRATE;

MOSFET DEVICES;

EID: 0041910808     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2003.815603     Document Type: Article

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