Advances in hardware architectures for image and video coding - A survey

Proceedings of the IEEE

Volumn 93, Issue 1, 2005, Pages 184-197

  Tseng, Po Chih ^a   Chang, Yung Chi ^a   Huang, Yu Wen ^a   Fang, Hung Chi ^a   Huang, Chao Tsung ^a   Chen, Liang Gee ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

H.264 AVC; Hardware architecture; Image coding; JPEG; MPEG 4; Very large scale integration (VLSI); Video coding

Indexed keywords

BLOCK CODES; CAMERAS; CODES (SYMBOLS); COMPUTER ARCHITECTURE; DATA REDUCTION; IMAGE CODING; IMAGE COMPRESSION; OPTIMIZATION; VLSI CIRCUITS;

H.264/AVC; HARDWARE ARCHITECTURE; JPEG 2000; MPEG-4; VERY LARGE SCALE INTEGRATION (VLSI);

COMPUTER HARDWARE;

EID: 20744450420     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/JPROC.2004.839622     Document Type: Review

References (103)

1. B. G. Haskell, P. G. Howard, Y. A. LeCun, A. Puri, J. Ostermann, M. R. Civanlar, L. Rabiner, L. Bottou, and P. Haffner, "Image and video coding - Emerging standards and beyond," IEEE Trans. Circuits Syst. Video Technol., vol. 8, no. 7, pp. 814-837, Nov. 1998.
2. "Information technology - Digital compression and coding of continuous-tone still images," Int. Standards Org./Int. Electrotech. Comm. (ISO/IEC) and Int. Telecommun. Union-Telecommun. (ITU-T), ISO/IEC 10918-1 and ITU-T Recommendation T.81, 1994.
3. "JPEG 2000 part 1 final draft international standard," Int. Standards Org./Int. Electrotech. Comm. (ISO/IEC), ISO/IEC FDIS15 444-1, Dec. 2000.
4. "Information technology - Coding of moving pictures and associated audio for digital storage media at up to about 1.5 Mbit/s: Video," Int. Standards Org./Int. Electrotech. Comm. (ISO/IEC), ISO/IEC 11 172-2, 1994.
5. "Information technology - Generic coding of moving pictures and associated audio information: Video," Int. Standards Org./Int. Electrotech. Comm. (ISO/IEC) and Int. Telecommun. Union-Telecommun. (ITU-T), 13818-2 and ITU-T Recommendation H.262, 1996.
6. "Information technology - Coding of audio-visual objects - Part 2: Visual," Int. Standards Org./Int. Electrotech. Comm. (ISO/IEC), ISO/IEC 14496-2, 1999.
7. "Video codec for audiovisual services at p × 64 kbit/s," Int. Telecommun. Union-Telecommun. (ITU-T), Geneva, Switzerland, Recommendation H.261, 1993.
8. "Video coding for low bit rate communication," Int. Telecommun. Union-Telecommun. (ITU-T), Geneva, Switzerland, Recommendation H.263, 1998.
9. "Draft ITU-T Recommendation and final draft International Standard of Joint Video Specification," Joint Video Team, Int. Telecommun. Union-Telecommun. (ITU-T) and Int. Standards Org./Int. Electrotech. Comm. (ISO/IEC), ITU-T Recommendation H.264 and ISO/IEC 14496-10 AVC, May 2003.
10. P. Pirsch, N. Demassieux, and W. Gehrke, "VLSI architectures for video compression - A survey," Proc. IEEE, vol. 83, no. 2, pp. 220-246, Feb. 1995.
11. P. Pirsch and H.-J. Stolberg, "VLSI implementations of image and video multimedia processing systems," IEEE Trans. Circuits Syst. Video Technol., vol. 8, no. 7, pp. 878-891, Nov. 1998.
12. I. Kuroda and T. Nishitani, "Multimedia processors," Proc. IEEE, vol. 86, no. 6, pp. 1203-1221, Jun. 1998.
13. A. Dasu and S. Panchanathan, "A survey of media processing approaches," IEEE Trans. Circuits Syst. Video Technol., vol. 12, no. 8, pp. 633-645, Aug. 2002.
14. V. Lappalainen, T. D. Hamalainen, and P. Liuha, "Overview of research efforts on media ISA extensions and their usage in video coding," IEEE Trans. Circuits Syst. Video Technol., vol. 12, no. 8, pp. 660-670, Aug. 2002.
15. T. Sikora, "The MPEG-4 video standard verification model," IEEE Trans. Circuits Syst. Video Technol., vol. 7, no. 1, pp. 19-31, Feb. 1997.
16. T. Ebrahimi and C. Horne, "MPEG-4 natural video coding - An overview," Signal Process. Image Commun., vol. 15, no. 4-5, pp. 365-385, Jan. 2000.
17. P. M. Kuhn and W. Stechele, "Complexity analysis of the emerging MPEG-4 standard as a basis for VLSI implementation," in Proc. Int. Conf. Visual Communications and Image Processing, 1998, pp. 498-509.
18. H. C. Chang, L. G. Chen, M. Y. Hsu, and Y. C. Chang, "Performance analysis and architecture evaluation of MPEG-4 video codec system," in Proc. IEEE Int. Symp. Circuits and Systems, vol. 2, 2000, pp. 449-452.
19. H.-J. Stolberg, M. Berekovic, P. Pirsch, and H. Runge, "The MPEG-4 advanced simple profile - A complexity study," in Proc. Workshop and Exhibition on MPEG-4, 2001, pp. 33-36.
20. S. Y. Chien, C. Y. Chen, W. M. Chao, Y. W. Huang, and L. G. Chen, "Analysis and hardware architecture for global motion estimation in MPEG-4 advanced simple profile," in Proc. IEEE Int. Symp. Circuits and Systems, vol. 2, 2003, pp. 720-723.
21. C. W. Hsu, Y. C. Chang, W. M. Chao, and L. G. Chen, "Hardware- oriented optimization and block-level architecture design for MPEG-4 FGS encoder," in Proc. IEEE Int. Symp. Circuits and Systems, vol. 2, 2003, pp. 784-787.
22. T. Komarek and P. Pirsch, "Array architectures for block matching algorithms," IEEE Trans. Circuits Syst., vol. 36, no. 2, pp. 1301-1308, Oct. 1989.
23. L. D. Vos and M. Stegherr, "Parameterizable VLSI architectures for the full-search block-matching algorithm," IEEE Trans. Circuits Syst., vol. 36, no. 2, pp. 1309-1316, Oct. 1989.
24. K. M. Yang, M. T. Sun, and L. Wu, "A family of VLSI designs for the motion compensation block-matching algorithm," IEEE Trans. Circuits Syst., vol. 36, no. 2, pp. 1317-1325, Oct. 1989.
25. C. H. Hsieh and T. P. Lin, "VLSI architecture for block-matching motion estimation algorithm," IEEE Trans. Circuits Syst. Video Technol., vol. 2, no. 2, pp. 169-175, Jun. 1992.
26. H. Yeo and Y. H. Hu, "A novel modular systolic array architecture for full-search block matching motion estimation," IEEE Trans. Circuits Syst. Video Technol., vol. 5, no. 5, pp. 407-416, Oct. 1995.
27. Y. K. Lai and L. G. Chen, "A data-interlacing architecture with two-dimensional data-reuse for full-search block-matching algorithm," IEEE Trans. Circuits Syst. Video Technol., vol. 8, no. 2, pp. 124-127, Apr. 1998.
28. Y. H. Yeh and C. Y. Lee, "Cost-effective VLSI architectures and buffer size optimization for full-search block matching algorithms," IEEE Trans. Very Large Scale (VLSI) Syst., vol. 7, no. 3, pp. 345-358, Sep. 1999.
29. Y. S. Jehng, L. G. Chen, and T. D. Chiueh, "An efficient and simple VLSI tree architecture for motion estimation algorithms," IEEE Trans. Signal Process., vol. 41, no. 2, pp. 889-900, Feb. 1993.
30. H. M. Jong, L. G. Chen, and T. D. Chiueh, "Parallel architectures for 3-step hierarchical search block-matching algorithm," IEEE Trans. Circuits Syst. Video Technol., vol. 4, no. 4, pp. 407-416, Aug. 1994.
31. S. Dutta and W. Wolf, "A flexible parallel architecture adopted to block-matching motion estimation algorithms," IEEE Trans. Circuits Syst. Video Technol., vol. 6, no. 1, pp. 74-86, Feb. 1996.
32. M. Mizuno, Y. Ooi, N. Hayashi, J. Goto, M. Hozumi, K. Furuta, A. Shibayama, Y. Nakazawa, O. Ohnishi, S. Y. Zhu, Y. Yokoyama, Y. Katayama, H. Takano, N. Miki, Y. Senda, I. Tamitani, and M. Yamashina, "A 1.5-W single-chip MPEG-2 MP@ML video encoder with low power motion estimation and clocking," IEEE J. Solid-State Circuits, vol. 32, no. 11, pp. 1807-1816, Nov. 1997.
33. M. Takahashi, T. Nishikawa, M. Hamada, T. Takayanagi, H. Arakida, N. Machida, H. Yamamoto, T. Fujiyoshi, Y. Ohashi, O. Yamagishi, T. Samata, A. Asano, T. Terazawa, K. Ohmori, Y. Watanabe, H. Nakamura, S. Minami, T. Kuroda, and T. Furuyama, "A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme," IEEE J. Solid-State Circuits, vol. 33, no. 11, pp. 1772-1780, Nov. 1998.
34. J. H. Lee, K. W. Lim, B. C. Song, and J. B. Ra, "A fast multi-resolution block matching algorithm and its VLSI architecture for low bit-rate video coding," IEEE Trans. Circuits Syst. Video Technol., vol. 11, no. 12, pp. 1289-1301, Dec. 2001.
35. J. C. Tuan, T. S. Chang, and C. W. Jen, "On the data reuse and memory bandwidth analysis for full-search block-matching VLSI architecture," IEEE Trans. Circuits Syst. Video Technol., vol. 12, no. 1, pp. 61-72, Jan. 2002.
36. H. C. Chang, Y. C. Chang, Y. C. Wang, W. M. Chao, and L. G. Chen, "VLSI architecture design of MPEG-4 shape coding," IEEE Trans. Circuits Syst. Video Technol., vol. 12, no. 9, pp. 741-751, Sep. 2002.
37. M. Berekovic, K. Jacob, and P. Pirsch, "Architecture of a hardware module for MPEG-4 shape decoding," in Proc. IEEE Int. Symp. Circuits and Systems, vol. 1, 1999, pp. 157-160.
38. D. Gong and Y. He, "An efficient architecture for real-time content-based arithmetic coding," in Proc. IEEE Int. Symp. Circuits and Systems, vol. 3, 2000, pp. 515-518.
39. T. H. Tsai and C. P. Chen, "An efficient binary motion estimation algorithm and its architecture for MPEG-4 shape coding," in Proc. Int. Symp. Circuits and Systems, vol. 2, 2003, pp. 496-499.
40. J. Thinakaran, D. J. Ho, and N. Ling, "Fast shape decoding for MPEG-4 video," in Proc. IEEE Workshop Signal Processing Systems, 2000, pp. 110-119.
41. K. B. Lee, N. Y. C. Chang, H. Y. Chin, H. J. Hsu, and C. W. Jen, "Optimal frame memory and data transfer scheme for MPEG-4 shape coding," in Proc. IEEE Int. Conf. Consumer Electronics, 2003, pp. 164-165.
42. S. F. Chang and D. G. Messerschmitt, "Designing high-throughput VLC decoder, Part I - Concurrent VLSI architectures," IEEE Trans. Circuits Syst. Video Technol., vol. 2, no. 2, pp. 187-196, Jun. 1992.
43. H. D. Lin and D. G. Messerschmitt, "Designing a high-throughput VLC decoder, Part II - Parallel decoding methods," IEEE Trans. Circuits Syst. Video Technol., vol. 2, no. 2, pp. 197-206, Jun. 1992.
44. S. M. Lei and M. T. Sun, "An entropy coding system for digital HDTV applications," IEEE Trans. Circuits Syst. Video Technol., vol. 1, no. 1, pp. 147-155, Mar. 1991.
45. H. C. Chang, L. G. Chen, Y. C. Chang, and S. C. Huang, "A VLSI architecture design of VLC encoder for high data rate video/image coding," in Proc. IEEE Int. Symp. Circuits and Systems, vol. 4, 1999, pp. 398-401.
46. M. Novell and S. Molloy, "VLSI implementation of a reversible variable length encoder/decoder," in Proc. IEEE Int. Conf. Acoustics, Speech, and Signal Processing, vol, 4, 1999, pp. 1969-1972.
47. J. Y. Yang, Y. Lee, H. Lee, and J. Kim, "A variable length coding ASIC chip for HDTV video encoders " IEEE Trans. Consum. Electron., vol. 43, no. 3, pp. 633-638, Aug. 1997.
48. Y. Fukuzawa, K. Hasegawa, H. Hanaki, E. Iwata, and T. Yamazaki, "A programmable VLC core architecture for video compression DSP," in Proc. IEEE Workshop Signal Processing Systems, 1997, pp. 469-478.
49. S. H. Cho, T. Xanthopoulos, and A. P. Chandrakasan, "A low power variable length decoder for MPEG-2 based on nonuniform fine-grain table partitioning," IEEE Trans. Very Large Scale (VLSI) Syst., vol. 7, no. 2, pp. 249-257, Jun. 1999.
50. K. M. Yang, H. Fujiwara, T. Sakaguchi, and A. Shimazu, "VLSI architecture design of a versatile variable length decoding chip for real-time video codecs," in Proc. IEEE Conf. Computer and Communication Systems, vol. 2, 1990, pp. 551-554.
51. B. J. Shieh, Y. S. Lee, and C. Y. Lee, "A new approach of group-based VLC codec system with full table programmability," IEEE Trans. Circuits Syst. Video Technol., vol. 11, no. 2, pp. 210-221, Feb. 2001.
52. Y. Zhang and K. K. Ma, "An embedded RISC core design for variable length coding," in Proc. IEEE Int. Conf./Exhibition High Performance Computing in the Asia-Pacific Region, vol. 1, 2000, pp. 361-365.
53. M. Berekovic, H.-J. Stolberg, M. B. Kulaczewski, P. Pirsch, H. Moller, H. Runge, J. Kneip, and B. Stabernack, "Instruction set extensions for MPEG-4 video," J. VLSI Signal Process., vol. 23, no. 1.pp. 27-49, Oct. 1999.
54. H. C. Chang, Y. C. Chang, Y. B. Tsai, C. P. Fan, and L. G. Chen, "MPEG-4 video bitstream structure analysis and its parsing architecture design," in Proc. IEEE Int. Symp. Circuits and Systems, vol. 2. 2000, pp. 184-187.
55. Y. C. Chang, H. C. Chang, and L. G. Chen, "Design and implementation of a bitstream parsing coprocessor for MPEG-4 video system-on-chip solution," in Proc. IEEE Int. Symp. VLSI Technology, Systems, and Applications, 2001, pp. 188-191.
56. Y. C. Chang, C. C. Huang, W. M. Chao, and L. G. Chen, "An efficient embedded bitstream parsing processor for MPEG-4 video decoding system," in Proc. Int. Symp. VLSI Technology, Systems, and Applications, 2003, pp. 168-171.
57. M. Takahashi, M. Hamada, T. Nishikawa, H. Arakida, Y. Tsuboi, T. Fujita, F. Hatori, S. Mita, K. Suzuki, A. Chiba, T. Terazawa, F. Sano, Y. Watanabe, H. Momose, K. Usami, M. Igarashi, T. Ishikawa, M. Kanazawa, T. Kuroda, and T. Furuyama, "A 60 mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme," in Dig. Tech. Papers IEEE Int. Solid-State Circuits Conf., 1998, pp. 36-37.
58. T. Nishikawa, M. Takahashi, M. Hamada, T. Takayanagi, H. Arakida, N. Machida, H. Yamamoto, T. Fujiyoshi, Y. Maisumoto, O. Yamagishi, T. Samata, A. Asano, T. Terazawa, K. Ohmori, J. Shirakura, Y. Watanabe, H. Nakamura, S. Minami, T. Kuroda, and T. Furuyama, "A 60 MHz 240 mW MPEG-4 video-phone LSI with 16 Mb embedded DRAM," in Dig. Tech. Papers IEEE Int. Solid-State Circuits Conf., 2000, pp. 230-231.
59. T. Hashimoto, S. Kuromaru, M. Matsuo, K. Yasuo, T. Mori-iwa, K. Ishida, S. Kajita, M. Ohashi, M. Toujima, T. Nakamura, M. Hamada, T. Yonezawa, T. Kondo, K. Hashimoto, Y. Sugisawa, H. Otsuki, M. Arita, H. Nakajima, H. Fujimoto, J. Michiyama, Y. Lizuka, H. Komori, S. Nakatani, H. Toida, T. Takahashi, H. Ito, and T. Yukitake, "A 90 mW MPEG4 video codec LSI with the capability for core profile," in Dig. Tech. Papers IEEE Int. Solid-State Circuits Conf., 2001, pp. 140-141.
60. M. Ohashi, T. Hashimoto, S. Kuromaru, M. Matsuo, T. Mori-iwa, M. Hamada, Y. Sugisawa, M. Arita, H. Tomita, M. Hoshino, H. Miyajima, T. Nakamura, K. Ishida, T. Kimura, Y. Kohashi, T. Kondo, A. Inoue, H. Fujimoto, K. Watada, T. Fukunaga, T. Nishi, H. Ito, and J. Michiyama, "A 27 MHz 11.1 mW MPEG-4 video decoder LSI for mobile application," in Dig. Tech. Papers IEEE Int. Solid-State Circuits Conf., 2002, pp. 366-367.
61. H. Nakayama, T. Yoshitake, H. Komazaki, Y. Watanabe, H. Araki, K. Morioka, J. Li, L. Peilin, S. Lee, H. Kubosawa, and Y. Otobe, "An MPEG-4 video LSI with an error-resilient codec core based on a fast motion estimation algorithm," in Dig. Tech. Papers IEEE Int. Solid-State Circuits Conf., 2002, pp. 368-369.
62. H. Arakida, M. Takahashi, Y. Tsuboi, T. Nishikawa, H. Yamamoto, T. Fujiyoshi, Y. Kitasho, Y. Ueda, M. Watanabe, T. Fujita, T. Terazawa, K. Ohmori, M. Koana, H. Nakamura, E. Watanabe, H. Ando, T. Aikawa, and T. Furuyama, "A 160 mW, 80 nA standby, MPEG-4 audiovisual LSI with 16 mb embedded DRAM and a 5 GOPS adaptive post filter," in Dig. Tech. Papers IEEE Int. Solid-State Circuits Conf., 2003, pp. 1-11.
63. H.-J. Stolberg, S. Moch, L. Friebe, A. Dehnhardt, M. Kulaczewski, M. Berekovic, and P. Pirsch, "An SoC with two multimedia DSP's and a RISC core for video compression and surveillance," in Dig. Tech. Papers IEEE Int. Solid-State Circuits Conf., 2004, pp. 330-331.
64. C. Christopoulos, A. Skodras, and T. Ebrahimi, "The JPEG2000 still image coding system: An overview," IEEE Trans. Consum, Electron., vol. 46, no. 4, pp. 1103-1127, Nov. 2000.
65. A. Skodras, C. Christopoulos, and T. Ebrahimi, "The JPEG 2000 still image compression standard," IEEE Signal Process. Mag., vol. 18, no. 5, pp. 36-58, Sep. 2001.
66. D. S. Taubman and M. W. Marcellin, "JPEG2000: Standard for interactive imaging," Proc. IEEE, vol. 90, no. 8, pp. 1336-1357, Aug. 2002.
67. M. D. Adams and F. Kossentini, "JasPer: A software-based JPEG2000 codec implementation," in Proc. IEEE Int. Conf. Image Processing, vol. 2, 2000, pp. 53-56.
68. C. J. Lian, K. F. Chen, H. H. Chen, and L. G. Chen, "Analysis and architecture design of block-coding engine for EBCOT in JPEG 2000," IEEE Trans. Circuits Syst. Video Technol., vol. 13, no. 3, pp. 219-230, Mar. 2003.
69. T. H. Chang, L. L. Chen, C. J. Lian, H. H. Chen, and L. G. Chen, "Computation reduction technique for lossy JPEG2000 encoding through EBCOT tier-2 feedback processing," in Proc. IEEE Int. Conf. Image Processing, 2002, pp. 85-88.
70. T. H. Chang, C. J. Lian, H. H. Chen, J. Y. Chang, and L. G. Chen, "Effective hardware-oriented technique for the rate control of JPEG2000 encoding," in Proc. IEEE Int. Symp. Circuits and Systems, vol. 2, 2003, pp. 684-687.
71. Y. M. Yeung, O. C. Au, and A. Chang, "Efficient rate control technique for JPEG2000 image coding using priority scanning," in Proc. IEEE Int. Conf. Multimedia and Expo, vol. 3, 2003, pp. 277-280.
72. Y. W. Chang, H. C. Fang, C. J. Lian, and L. G. Chen, "Novel precompression rate-distortion optimization algorithm for JPEG 2000," in Proc. Int. Conf. Visual Communications and Image Processing, 2004.
73. S. G. Mallat, "A theory for multiresolution signal decomposition: The wavelet representation," IEEE Trans. Pattern Anal. Mach. Intell., vol. 11, no. 7, pp. 674-693, Jul. 1989.
74. C. Chakrabarti, M. Vishwanath, and R. M. Owens, "Architectures for wavelet transforms: A survey," J. VLSI Signal Process., vol. 14, pp. 171-192, 1996.
75. W. Sweldens, "The lifting scheme: A custom-design construction of biorthogonal wavelets," Appl. Comput. Harmonic Anal., vol. 3, no. 15, pp. 186-200, 1996.
76. I. Daubechies and W. Sweldens, "Factoring wavelet transforms into lifting steps," J. Fourier Anal. Appl., vol. 4, pp. 247-269, 1998.
77. K. Andra, C. Chakrabarti, and T. Acharya, "A VLSI architecture for lifting-based forward and inverse wavelet transform," IEEE Trans. Signal Process., vol. 50, no. 4, pp. 966-977, Apr. 2002.
78. C. T. Huang, P. C. Tseng, and L. G. Chen, "Flipping structure: An efficient VLSI architecture for lifting-based discrete wavelet transform," IEEE Trans. Signal Process., to be published.
79. M. Unser and T. Blu, "Wavelet theory demystified," IEEE Trans. Signal Process., vol. 51, no. 2, pp. 470-483, Feb. 2003.
80. C. T. Huang, P. C. Tseng, and L. G. Chen, "VLSI architecture for forward discrete wavelet transform based on B-spline factorization," J. VLSI Signal Process., to be published.
81. N. D. Zervas, G. P. Anagnostopoulos, V. Spiliotopoulos, Y. Andreopoulos, and C. E. Goutis, "Evaluation of design alternatives for the 2-D-discrete wavelet transform," IEEE Trans. Circuits Syst. Video Technol., vol. 11, no. 12, pp. 1246-1262, Dec. 2001.
82. C. Chrysafis and A. Ortega, "Line-based, reduced memory, wavelet image compression," IEEE Trans. Image Process., vol. 9, no. 3, pp. 378-389, Mar. 2000.
83. P. C. Wu and L. G. Chen, "An efficient architecture for two-dimensional discrete wavelet transform," IEEE Trans. Circuits Syst. Video Technol., vol. 11, no. 4, pp. 536-545, Apr. 2001.
84. W. Jiang and A. Ortega, "Lifting factorization-based discrete wavelet transform architecture design," IEEE Trans. Circuits Syst. Video Technol., vol. 11, no. 5, pp. 651-657, May 2001.
85. D. Taubman, "High performance scalable image compression with EBCOT," IEEE Trans. Image Process., vol. 9, no. 7, pp. 1158-1170, Jul. 2000.
86. D. Taubman, E. Ordentlich, M. Weinberger, and G. Seroussi, "Embedded block coding in JPEG 2000," Signal Process. Image Commun., vol. 17, no. 1, pp. 49-72, Jan. 2002.
87. "JPEG 2000 verification model 7.0 (technical description)," Int. Standards Org./Int. Electrotech. Comm. (ISO/IEC), ISO/IEC JTC1/SC29/WG1 N1684, Apr. 2000.
88. H. H. Chen, C. J. Lian, T. H. Chang, and L. G. Chen, "Analysis of EBCOT decoding algorithm and its VLSI implementation for JPEG 2000," in Proc. IEEE Int. Symp. Circuits and Systems, vol. 4, 2002, pp. 329-332.
89. Y. T. Hsiao, H. D. Lin, K. B. Lee, and C. W. Jen, "High-speed memory saving architecture for the embedded block coding in JPEG2000," in P roc. IEEE Int. Symp. Circuits and Systems, vol. 5, 2002, pp. 133-136.
90. J. S. Chiang, Y. S. Lin, and C. Y. Hsieh, "Efficient pass-parallel architecture for EBCOT in JPEG2000," in Proc. IEEE Int. Symp. Circuits and Systems, vol. 1, 2002, pp. 773-776.
91. H. Yamauchi, S. Okada, K. Taketa, T. Ohyama, Y. Matsuda, T. Mon, T. Watanabe, Y. Matsuo, Y. Yamada, T. Ichikawa, and Y. Matsushita, "Image processor capable of block-noise-free JPEG2000 compression with 30 frames/s for digital camera applications," in Dig. Tech. Papers IEEE Int. Solid-State Circuits Conf, 2003, pp. 46-47.
92. H. C. Fang, T. C. Wang, Y. W. Chang, Y. Y. Shih, and L. G. Chen, "Novel word-level algorithm of embedded block coding in JPEG 2000," in Proc. IEEE Int. Conf. Multimedia and Expo, vol. 1, 2003, pp. 137-140.
93. H. C. Fang, T. C. Wang, C. J. Lian, T. H. Chang, and L. G. Chen, "High speed memory efficient EBCOT architecture for JPEG2000," in Proc. IEEE Int. Symp. Circuits and Systems, vol. 2, 2003, pp. 736-739.
94. DSPworx Cheetah [Online]. Available: http://www.dspworx. com/cheetah.htm
95. K. Andra, C. Chakrabarti, and T. Acharya, "A high-performance JPEG2000 architecture," IEEE Trans. Circuits Syst. Video Technol., vol. 13, no. 3, pp. 209-218, Mar. 2003.
96. Analog Devices Inc. ADV202 [Online]. Available: http://www.analog.com/
97. H. C. Fang, C. T. Huang, Y. W. Chang, T. C. Wang, P. C. Tseng, C. J. Lian, and L. G. Chen, "81 MS/s JPEG 2000 single-chip encoder with rate-distortion optimization," in Dig. Tech. Papers IEEE Int. Solid-State Circuits Conf., 2004, p. 328.
98. ALMA Technologies JPEG2KE [Online]. Available: http://www.alma-tech.com/
99. AMPHION CS6590 [Online]. Available: http://www.amphion. com/cs6590.html
100. T. Wiegand, G. J. Sullivan, G. Bjntegaard, and A. Luthra, "Overview of the H.264/AVC video coding standard," IEEE Trans. Circuits Syst. Video Technol., vol. 13, no. 7, pp. 560-576, Jul. 2003.
101. T. Wiegand, H. Schwarz, A. Joch, F. Kossentini, and G. J. Sullivan, "Rate-constrained coder control and comparison of video coding standards," IEEE Trans. Circuits Syst. Video Technol., vol. 13, no. 7, pp. 688-703, Jul. 2003.
102. K. Denolf, C. Blanch, G. Lafruit, and A. Bormans, "Initial memory complexity analysis of the AVC codec," in Proc. IEEE Workshop Signal Processing Systems, 2002, pp. 222-227.
103. V. Lappalainen, A. Hallapuro, and T. D. Hamalainen, "Performance of H.26L video encoder on general-purpose processor," J. VLSI Signal Process., vol. 34, no. 3, pp. 239-249, Jul. 2003.