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Volumn 7, Issue 3, 1999, Pages 345-358

Cost-effective VLSI architectures and buffer size optimization for full-search block matching algorithms

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BUFFER CIRCUITS; COMPUTER SIMULATION; ELECTRIC NETWORK ANALYSIS; GRAPH THEORY; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION;

EID: 0032684816     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.784096     Document Type: Article
Times cited : (30)

References (17)
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  • 8
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    • A high-throughput and flexible VLSI architecture for motion estimation
    • Detroit, MI, May 8-12
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.