Cost-effective VLSI architectures and buffer size optimization for full-search block matching algorithms

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 7, Issue 3, 1999, Pages 345-358

  Yeh, Yuan Hau ^b   Lee, Chen Yi ^a,b  

^a IEEE

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BUFFER CIRCUITS; COMPUTER SIMULATION; ELECTRIC NETWORK ANALYSIS; GRAPH THEORY; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION;

FULL-SEARCH BLOCK MATCHING ALGORITHMS;

VLSI CIRCUITS;

EID: 0032684816     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.784096     Document Type: Article

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