Evaluation of design alternatives for the 2-D-discrete wavelet transform

IEEE Transactions on Circuits and Systems for Video Technology

Volumn 11, Issue 12, 2001, Pages 1246-1262

  Zervas, Nikos D ^a   Anagnostopoulos, Giorgos P ^a   Spiliotopoulos, Vassilis ^a   Andreopoulos, Yiannis ^b   Goutis, Costas E ^a  

^a UNIVERSITY OF PATRAS   (Greece)

^b VRIJE UNIVERSITEIT BRUSSEL   (Belgium)

Author keywords

2 D DWT; Comparative study; VLSI architectures

Indexed keywords

ALGORITHMS; DIGITAL STORAGE; ENERGY DISSIPATION; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION; THROUGHPUT; VLSI CIRCUITS;

DISCRETE WAVELET TRANSFORMS (DWT);

WAVELET TRANSFORMS;

EID: 0035694036     PISSN: 10518215     EISSN: None     Source Type: Journal    
DOI: 10.1109/76.974679     Document Type: Article

References (16)

1. VLSI architecture for the discrete wavelet transform
2. VLSI architectures for discrete wavelet transforms
3. VLSI architectures for the discrete wavelet transform
4. Scalable VLSI architectures for lattice structure-based discrete wavelet transform
5. Architectures for wavelet transform: A survey
6. Optimal memory organizations for scalable texture codecs in MPEG-4
7. Multifrequency chanel decompositions of images and wavelet models
8. Architectural power analysis: The dual bit type method
9. Trends in low-power RAM circuit technologies
10. An efficient VLSI architecture for separable 2-D discrete wavelet transform
11. Line-based, reduced memory, wavelet image compression