A data-interlacing architecture with two-dimensional data-reuse for full-search block-matching algorithm

IEEE Transactions on Circuits and Systems for Video Technology

Volumn 8, Issue 2, 1998, Pages 124-127

  Lai, Yeong Kang ^a   Chen, Liang Gee ^b  

^a CHANG GUNG UNIVERSITY   (Taiwan)

^b NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

Architecture; Blocking matching algorithm; Motion estimation; Video coding; VLSI

Indexed keywords

ALGORITHMS; DATA STRUCTURES; EFFICIENCY; ESTIMATION; MOTION CONTROL; VLSI CIRCUITS;

MOTION ESTIMATION;

VIDEO SIGNAL PROCESSING;

EID: 0032047902     PISSN: 10518215     EISSN: None     Source Type: Journal    
DOI: 10.1109/76.664095     Document Type: Article

References (6)

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