A 90mW MPEG4 video codec LSI with the capability for core profile

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2001, Pages 140-141+440

  Hashimoto, T ^a   Kuromaru, S I ^a   Matsuo, M ^a   Kohashi, Y ^a   Mori Iwa, T ^a   Ishida, K I ^a   Kajita, S ^a   Ohashi, M ^a   Toujima, M ^a   Nakamura, T ^a   Hamada, M ^a   Yonezawa, T ^a   Kondo, T ^a   Hashimoto, K ^a   Sugisawa, Y ^a   Otsuki, H ^a   Arita, M ^a   Nakajima, H ^a   Fujimoto, H ^a   Michiyama, J ^a   Iizuka, Y ^a   Komori, H ^a   Nakatani, S ^a   Toida, H ^a   Takahashi, T ^a   Ito, H ^a   Yukitake, T ^a   more..

^a PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE ALGORITHMS; COMPUTER ARCHITECTURE; DIGITAL SIGNAL PROCESSING; DYNAMIC RANDOM ACCESS STORAGE; IMAGE CODING; INTERFACES (COMPUTER); MOTION ESTIMATION; PROGRAM PROCESSORS;

HARDWARE ENGINES; MOBILE VIDEO; POWER CONSUMPTION;

LSI CIRCUITS;

EID: 0035060904     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. A 60MHz 240mW MPEG-4 video-phone LSI with 16Mb embedded DRAM
2. Media processor core architecture for realtime, bi-directional MPEG4/H.26X codec with 30fr/s for CIF-Video
3. A MPEG4 programmable codec DSP with an embedded pre/post-processing engine