High-speed memory-saving architecture for the embedded block coding in JPEG2000

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 2002, Pages

  Hsiao, Yun Tai ^a   Lin, Hung Der ^a   Lee, Kun Bin ^a   Jen, Chein Wei ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; IMAGE CODING; IMAGE COMPRESSION; MICROPROCESSOR CHIPS; STANDARDS;

EMBEDDED BLOCK CODING; HIGH-SPEED MEMORY-SAVING ARCHITECTURE; JOINT PICTURE EXPERTS GROUP; RENORMALIZATION STRATEGY;

LOGIC DESIGN;

EID: 0036294939     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. The JPEG2000 still image coding system: An overview
2. An analytical study of JPEG2000 functionalities
3. Embedded block coding in JPEG 2000
4. High performance scalable image compression with EBCOT
5. Analysis and architecture design of EBCOT for JPEG-2000
6. Analysis and architecture design of lifting based DWT and EBCOT for JPEG 2000
7. High-speed implementation of JBIG arithmetic coder