A 1.5-W single-chip MPEG-2 MP@ML video encoder with low power motion estimation and clocking

IEEE Journal of Solid-State Circuits

Volumn 32, Issue 11, 1997, Pages 1807-1816

  Mizuno, Masayuki ^a,b,c,d   Ooi, Yasushi ^a,b   Hayashi, Naoya ^b   Goto, Junichi ^b   Hozumi, Masatoshi ^b   Furuta, Koichiro ^b   Shibayama, Atsufumi ^b   Nakazawa, Yoetsu ^b   Ohnishi, Osamu ^b   Zhu, Shu Yu ^b   Yokoyama, Yutaka ^b   Katayama, Yoichi ^b   Takano, Hideto ^b   Miki, Noriyuki ^b   Senda, Yuzo ^a,b   Tamitani, Ichiro ^b   Yamashina, Masakazu ^a,b  

^a IEEE   (Japan)

^b NEC CORPORATION   (Japan)

^c OSAKA UNIVERSITY   (Japan)

^d Institute of Electronics   (Japan)

Author keywords

Clocking; Low power; Motion estimation; MPEG 2; Phase locked loop; Single chip; Systolic array; Video compression; Video encoder

Indexed keywords

CMOS INTEGRATED CIRCUITS; FLIP FLOP CIRCUITS; IMAGE CODING; IMAGE COMPRESSION; MICROPROCESSOR CHIPS; PHASE LOCKED LOOPS; RANDOM ACCESS STORAGE; REAL TIME SYSTEMS; SYSTOLIC ARRAYS;

MOTION ESTIMATION; MPEG 2 ENCODER SYSTEM; VIDEO ENCODER;

LSI CIRCUITS;

EID: 0031276852     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.641704     Document Type: Article

References (10)

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